Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
PCU – Serial Peripheral Interface (SPI)
1038
Datasheet
A status bit indicates when the cycle has completed on the SPI port allowing the host to
know when read results can be checked and/or when to initiate a new command.
know when read results can be checked and/or when to initiate a new command.
The controller also provides the “Atomic Cycle Sequence” for performing erases and
writes to the SPI Flash. When this bit is 1 (and the Go bit is written to 1), a sequence of
cycles is performed on the SPI interface without allowing other SPI device to arbitrate
and interleave cycles to the Flash device. In this case, the specified cycle is preceded
by the Prefix Command (8-bit programmable Opcode) and followed by repeated reads
to the Status Register (Opcode 05h) until bit 0 indicates the cycle has completed. The
hardware does not attempt to check that the programmed cycle is a write or erase.
writes to the SPI Flash. When this bit is 1 (and the Go bit is written to 1), a sequence of
cycles is performed on the SPI interface without allowing other SPI device to arbitrate
and interleave cycles to the Flash device. In this case, the specified cycle is preceded
by the Prefix Command (8-bit programmable Opcode) and followed by repeated reads
to the Status Register (Opcode 05h) until bit 0 indicates the cycle has completed. The
hardware does not attempt to check that the programmed cycle is a write or erase.
If a Programmed Access is initiated (Cycle Go written to 1) while the SPI controller is
already busy with a Direct Memory Read, then the SPI Host hardware will hold the new
Programmed Access pending until the preceding SPI access completes.
already busy with a Direct Memory Read, then the SPI Host hardware will hold the new
Programmed Access pending until the preceding SPI access completes.
Once the SPI controller has committed to running a programmed access, subsequent
writes to the programmed cycle registers that occur before it has completed will not
modify the original transaction and will result in the assertion of the FCERR bit.
Software should never purposely behave in this way and rely on this behavior. However,
the FCERR bit provides basic error-reporting in this situation. Writes to the following
registers cause the FCERR bit assertion in this situation:
writes to the programmed cycle registers that occur before it has completed will not
modify the original transaction and will result in the assertion of the FCERR bit.
Software should never purposely behave in this way and rely on this behavior. However,
the FCERR bit provides basic error-reporting in this situation. Writes to the following
registers cause the FCERR bit assertion in this situation:
•
Software Sequencing Control
•
Software Sequencing Address
•
SPI Data
With the exception of Illegal Opcodes, the SPI controller does not police which opcodes
are valid to be used in SW Sequencing. For example, if SW programs a Dual Output
Fast Read opcode, then the Dual Output Fast Read cycle will be issued, independent of
whether the Dual Output Fast Read enable bit was set in the component descriptor
section.
are valid to be used in SW Sequencing. For example, if SW programs a Dual Output
Fast Read opcode, then the Dual Output Fast Read cycle will be issued, independent of
whether the Dual Output Fast Read enable bit was set in the component descriptor
section.