Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
PCU – System Management Bus (SMBus)
1094
Datasheet
If the processor sees that it has lost arbitration, the condition is called a collision. The
processor will set SMB_Mem_HSTS.BERR, and if enabled, generate an interrupt or
SMI#. The processor is responsible for restarting the transaction.
processor will set SMB_Mem_HSTS.BERR, and if enabled, generate an interrupt or
SMI#. The processor is responsible for restarting the transaction.
The processor, as a SMBus master, drives the clock. When the processor is sending
address or command or data bytes on writes, it drives data relative to the clock it is
also driving. It will not start toggling the clock until the start or stop condition meets
proper setup and hold time. The processor will also ensure minimum time between
SMBus transactions as a master.
address or command or data bytes on writes, it drives data relative to the clock it is
also driving. It will not start toggling the clock until the start or stop condition meets
proper setup and hold time. The processor will also ensure minimum time between
SMBus transactions as a master.
22.2.3
Bus Timing
22.2.3.1
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the
processor as an SMBus master would like. They have the capability of stretching the
low time of the clock. When the processor attempts to release the clock (allowing the
clock to go high), the clock will remain low for an extended period of time.
processor as an SMBus master would like. They have the capability of stretching the
low time of the clock. When the processor attempts to release the clock (allowing the
clock to go high), the clock will remain low for an extended period of time.
The processor monitors the SMBus clock line after it releases the bus to determine
whether to enable the counter for the high time of the clock. While the bus is still low,
the high time counter must not be enabled. Similarly, the low period of the clock can be
stretched by an SMBus master if it is not ready to send or receive data.
whether to enable the counter for the high time of the clock. While the bus is still low,
the high time counter must not be enabled. Similarly, the low period of the clock can be
stretched by an SMBus master if it is not ready to send or receive data.
22.2.3.2
Bus Time Out (Processor as SMBus Master)
If there is an error in the transaction, such that an SMBus device does not signal an
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. The processor will discard the cycle and set the SMB_Mem_HSTS.DEVERR
bit. The time-out minimum is 25 ms (800 RTC clocks). The time-out counter inside the
processor will start after the last bit of data is transferred by the processor and it is
waiting for a response.
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. The processor will discard the cycle and set the SMB_Mem_HSTS.DEVERR
bit. The time-out minimum is 25 ms (800 RTC clocks). The time-out counter inside the
processor will start after the last bit of data is transferred by the processor and it is
waiting for a response.
The 25-ms time-out counter will not count under the following conditions:
1. The SMB_Mem_HSTS.BYTE_DONE_STS bit is set
2. The TCO_STS.SECOND_TO_STS bit is not set (this indicates that the system has
not locked up).
22.2.4
Interrupts / SMI#
The processor SMBus controller uses INTB as its virtual interrupt wire. However, the
system can alternatively be set up to generate SMI# instead of an interrupt, by setting
the SMB_Config_HCFG.SMI_EN bit.
system can alternatively be set up to generate SMI# instead of an interrupt, by setting
the SMB_Config_HCFG.SMI_EN bit.
The following tables specify how the various enable bits in the SMBus function control
the generation of the interrupt and Host SMI internal signals. The rows in the tables are
additive, which means that if more than one row is true for a particular scenario then
the results for all of the activated rows will occur.
the generation of the interrupt and Host SMI internal signals. The rows in the tables are
additive, which means that if more than one row is true for a particular scenario then
the results for all of the activated rows will occur.