Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
Datasheet
1101
PCU – System Management Bus (SMBus)
22.6.3
D31_F3_Command (SMB_Config_CMD)—Offset 4h
CMD register enables/disables memory/io space access and interrupt
Access Method
Default: 0000h
Type: PCI Configuration Register
(Size: 16 bits)
SMB_Config_CMD: [B:0, D:31, F:3] + 4h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSV
INTD
FBE
SER
R
WCC
PER
VG
AP
S
PM
WE
SC
E
BME
MSE
IOSE
Bit
Range
Default &
Access
Description
15:11
00000b
RO
Reserved (RSV): Reserved
10
0b
RW
INTD: Interrupt disable - 1 Disable SMBus to assert its interrupt
9
0b
RO
FBE: FBE - reserved as '0'
8
0b
RO
SERR: SERR enable - reserved as '0'
7
0b
RO
Wait Cycle Ctrl (WCC): Wait cycle control - reserved as '0'
6
0b
RO
Parity error response (PER): Parity error - reserved as '0'
5
0b
RO
VGA palette snnop (VGAPS): VGA palette snoop - reserved as '0'
4
0b
RO
PMWE: Postable Memory Write Enable - reserved as '0'
3
0b
RO
SCE: Special Cycle Enable - reserved as '0'
2
0b
RO
BME: Bus Master Enable - reserved as '0'
1
0b
RW
MSE: Memory space enable - 1 enables access to the SM Bus memory space registers
as defined by the Base Address Registes
0
0b
RW
IOSE: I/O space enable - 1 enables access to the SM Bus I/O space registers as defined
by the Base Address Register