Intel G1620T CM8063701448300 User Manual

Datasheet

113

DRAM0_BS[2:0]

O

DDR3

Bank Select: These signals define which banks are selected 

within each DRAM rank

DRAM0_RAS#

O

DDR3

Row Address Select: Used with DRAM0_CAS# and 

DRAM0_WE# (along with DRAM0_CS#) to define the DRAM 

Commands

DRAM0_CAS#

O

DDR3

Column Address Select: Used with DRAM0_RAS# and 

DRAM0_WE# (along with DRAM0_CS#) to define the SRAM 

Commands

DRAM0_WE#

O

DDR3

Write Enable Control Signal: Used with DRAM0_WE# and 

DRAM0_CAS# (along with control signal, DRAM0_CS#) to 

define the DRAM Commands.

DRAM0_DQ[63:0]

I/O

DDR3

Data Lines: Data signal interface to the DRAM data bus

DRAM0_DM[7:0]

O

DDR3

Data Mask: DM is an output mask signal for write data. Output 

data is masked when DM is sampled HIGH coincident with that 

output data during a Write access. DM is sampled on both 

edges of DQS.

DRAM0_DQSP[7:0]

DRAM0_DQSN[7:0]

I/O

DDR3

Data Strobes: The data is captured at the crossing point of 

each ‘P’ and its compliment ‘N’ during read and write 

transactions.
For reads, the strobe crossover and data are edge aligned, 

whereas in the Write command, the strobe crossing is in the 

centre of the data window.

DRAM0_ODT[2,0]

O

DDR3

On Die Termination: ODT signal going to DRAM in order to 

turn ON the DRAM ODT during Write.

DRAM_RCOMP[2]

O

Analog

Resistor Compensation: This signal needs to be terminated 

to VSS on board. This external resistor termination scheme is 

used for Resistor compensation of DRAM ODT strength.

DRAM_RCOMP[1]

O

Analog

Resistor Compensation: This signal needs to be terminated 

to VSS on board. This external resistor termination scheme is 

used for Resistor compensation of DQ buffers

DRAM_RCOMP[0]

O

Analog

Resistor Compensation: This signal needs to be terminated 

to VSS on board. This external resistor termination scheme is 

used for Resistor compensation of CMD buffers.

DRAM_VREF

I

Analog

Reference Voltage: DRAM interface Reference Voltage

DRAM_CORE_PWROK

I

Asynchrono

us CMOS

Core Power OK: This signal indicates the status of the DRAM 

Core power supply (power on in S0).

DRAM_VDD_S4_PWROK

I

Asynchrono

us CMOS

VDD Power OK: Asserted once the VRM is settled. Used 

primarily in the DRAM PHY to determine S3 state.

DRAM0_DRAMRST#

O

DRAM Reset: This signal is used to reset DRAM devices.

ICLK_DRAM_TERM
[1:0]

I/O

Pull-down to VSS through an 100kOhm 1% resistor.