Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
Datasheet
1183
PCU – iLB – Low Pin Count (LPC) Bridge
Note:
The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol
where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This
specification explicitly states that this protocol only applies to entry/exit of low-power
states which does not include asynchronous reset events. The processor asserts both
PMC_SUS_STAT# (connects to LPCPD#) and ILB_PLTRST# (connects to LRST#) at the
same time during a global reset. This is not inconsistent with the LPC LPCPD# protocol.
where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This
specification explicitly states that this protocol only applies to entry/exit of low-power
states which does not include asynchronous reset events. The processor asserts both
PMC_SUS_STAT# (connects to LPCPD#) and ILB_PLTRST# (connects to LRST#) at the
same time during a global reset. This is not inconsistent with the LPC LPCPD# protocol.
24.2.6.2
Clock Run (CLKRUN)
When there are no pending LPC cycles, and SERIRQ is in quiet mode, the processor can
shut down the LPC clock. The processor indicates that the LPC clock is going to shut
down by de-asserting the ILB_LPC_CLKRUN# signal. LPC devices that require the clock
to stay running should drive ILB_LPC_CLKRUN# low within 4 clocks of its de-assertion.
If no device drives the signal low within 4 clocks, the LPC clock will stop. If a device
asserts ILB_LPC_CLKRUN#, the processor will start the LPC clock and assert
ILB_LPC_CLKRUN#.
shut down the LPC clock. The processor indicates that the LPC clock is going to shut
down by de-asserting the ILB_LPC_CLKRUN# signal. LPC devices that require the clock
to stay running should drive ILB_LPC_CLKRUN# low within 4 clocks of its de-assertion.
If no device drives the signal low within 4 clocks, the LPC clock will stop. If a device
asserts ILB_LPC_CLKRUN#, the processor will start the LPC clock and assert
ILB_LPC_CLKRUN#.
Note:
The CLKRUN protocol is disabled by default. See
for further details.
24.2.7
Serialized IRQ (SERIRQ)
24.2.7.1
Overview
The interrupt controller supports a serial IRQ scheme. The signal used to transmit this
information is shared between the interrupt controller and all peripherals that support
serial interrupts. The signal line, ILB_LPC_SERIRQ, is synchronous to LPC clock, and
follows the sustained tri-state protocol that is used by LPC signals. The serial IRQ
protocol defines this sustained tri-state signaling in the following fashion:
information is shared between the interrupt controller and all peripherals that support
serial interrupts. The signal line, ILB_LPC_SERIRQ, is synchronous to LPC clock, and
follows the sustained tri-state protocol that is used by LPC signals. The serial IRQ
protocol defines this sustained tri-state signaling in the following fashion:
•
S – Sample Phase: Signal driven low
•
R – Recovery Phase: Signal driven high
•
T – Turn-around Phase: Signal released
The interrupt controller supports 21 serial interrupts. These represent the 15 ISA
interrupts (IRQ0–1, 3–15), the four PCI interrupts, and the control signals SMI# and
IOCHK#. Serial interrupt information is transferred using three types of frames:
interrupts (IRQ0–1, 3–15), the four PCI interrupts, and the control signals SMI# and
IOCHK#. Serial interrupt information is transferred using three types of frames:
•
Start Frame: ILB_LPC_SERIRQ line driven low by the interrupt controller to indicate
the start of IRQ transmission
the start of IRQ transmission
•
Data Frames: IRQ information transmitted by peripherals. The interrupt controller
supports 21 data frames.
supports 21 data frames.
•
Stop Frame: ILB_LPC_SERIRQ line driven low by the interrupt controller to indicate
end of transmission and next mode of operation.
end of transmission and next mode of operation.
24.2.7.2
Start Frame
The serial IRQ protocol has two modes of operation which affect the start frame: