Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
Serial ATA (SATA)
136
Datasheet
13.2.2
Theory of Operation
13.2.2.1
Standard ATA Emulation
The processor contains a set of registers that shadow the contents of the legacy IDE
registers. The behavior of the Command and Control Block registers, PIO, and DMA
data transfers, resets, and interrupts are all emulated.
registers. The behavior of the Command and Control Block registers, PIO, and DMA
data transfers, resets, and interrupts are all emulated.
Note:
The processor will assert INTR when the master device completes the EDD command
regardless of the command completion status of the slave device. If the master
completes EDD first, an INTR is generated and BSY will remain '1' until the slave
completes the command. If the slave completes EDD first, BSY will be '0' when the
master completes the EDD command and asserts INTR. Software must wait for busy to
clear (0) before completing an EDD command, as required by the ATA5 through ATA7
(T13) industry standards.
regardless of the command completion status of the slave device. If the master
completes EDD first, an INTR is generated and BSY will remain '1' until the slave
completes the command. If the slave completes EDD first, BSY will be '0' when the
master completes the EDD command and asserts INTR. Software must wait for busy to
clear (0) before completing an EDD command, as required by the ATA5 through ATA7
(T13) industry standards.
13.2.2.2
48-Bit LBA Operation
The SATA host controller supports 48-bit LBA through the host-to-device register FIS
when accesses are performed using writes to the task file. The SATA host controller will
ensure that the correct data is put into the correct byte of the host-to-device FIS.
when accesses are performed using writes to the task file. The SATA host controller will
ensure that the correct data is put into the correct byte of the host-to-device FIS.
There are special considerations when reading from the task file to support 48-bit LBA
operation. Software may need to read all 16-bits. Since the registers are only 8-bits
wide and act as a FIFO, a bit must be set in the device/control register, which is at
offset 3F6h for primary and 376h for secondary (or their native counterparts).
operation. Software may need to read all 16-bits. Since the registers are only 8-bits
wide and act as a FIFO, a bit must be set in the device/control register, which is at
offset 3F6h for primary and 376h for secondary (or their native counterparts).
If software clears Bit 7 of the control register before performing a read, the last item
written will be returned from the FIFO. If software sets Bit 7 of the control register
before performing a read, the first item written will be returned from the FIFO.
written will be returned from the FIFO. If software sets Bit 7 of the control register
before performing a read, the first item written will be returned from the FIFO.
Table 99. SATA/AHCI Feature Matrix
Feature
AHCI Disabled
AHCI Enabled
Native Command Queuing (NCQ)
N/A
Supported
Auto Activate for DMA
N/A
Supported
Hot Plug Support
N/A
Supported
Asynchronous Signal Recovery
N/A
Supported
3 Gb/s Transfer Rate
Supported
Supported
ATAPI Asynchronous Notification
N/A
Supported
Host & Link Initiated Power Management
N/A
Supported
Staggered Spin-Up
Supported
Supported
Command Completion Coalescing
N/A
N/A