Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
Datasheet
173
Serial ATA (SATA)
13.6.3
Primary Descriptor Table Pointer (PDTP)—Offset 4h
Access Method
Default: 00000000h
13.6.4
Secondary Command (SCMD)—Offset 8h
Access Method
Default: 00h
Type: I/O Register
(Size: 32 bits)
PDTP: [LBAR] + 4h
LBAR Type: PCI Configuration Register (Size: 32 bits)
LBAR Reference: [B:0, D:19, F:0] + 20h
LBAR Reference: [B:0, D:19, F:0] + 20h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DB
A
RSV
D
0
Bit
Range
Default &
Access
Description
31:2
00000000h
RW
Descriptor Base Address (DBA): Corresponds to A[31:2]. This table must not cross a
64K boundary in memory. When read, the current value of the pointer is returned
1:0
0b
RO
RSVD0: Reserved
Type: I/O Register
(Size: 8 bits)
SCMD: [LBAR] + 8h
LBAR Type: PCI Configuration Register (Size: 32 bits)
LBAR Reference: [B:0, D:19, F:0] + 20h
LBAR Reference: [B:0, D:19, F:0] + 20h
7
4
0
0
0
0
0
0
0
0
0
RSV
D
0
RWC
RSV
D
1
ST
A
R
T
Bit
Range
Default &
Access
Description
7:4
0b
RO
RSVD0: Reserved
3
0h
RW
Read / Write Control (RWC): Sets the direction of the bus master transfer: 0 =
memory to device, 1 = device to memory. This bit must not be changed when the bus
master function is active.
2:1
0b
RO
RSVD1: Reserved
0
0h
RW
Start/Stop Bus Master (START): Setting this bit enables bus master operation of the
controller. Bus master operation does not actually start unless the Bus Master Enable bit
in PCI configuration space is also set. Clearing it halts bus master operation.