Intel G1620T CM8063701448300 User Manual

Product codes
CM8063701448300
Page of 1272
Datasheet
53
Mapping Address Spaces
4.1.2
IO Fabric (MMIO) Map
Memory accesses targeting MMIO are routed by the IO fabric to programmed PCI 
ranges, or routed to the PCU by default (subtractive agent). Programmed PCI ranges 
can be moved within low or high MMIO, and most can be disabled.
Note:
Not all devices can be mapped to high MMIO.
Fixed MMIO is claimed by the Platform Controller Unit (PCU). The default regions are 
listed below. Movable ranges are not shown. See the register maps of all PCU devices 
for details.
The following PCI devices may claim memory resources in MMIO space:
Graphics/Display (High MMIO capable)
PCI Express* (High MMIO capable)
SATA
HD Audio
Platform Controller Unit (PCU) (Multiple BARs)
xHCI USB
EHCI USB
See each device’s interface chapter for details.
Warning: Variable memory ranges should not be set to conflict with other memory ranges. There 
will be unpredictable results if the configuration software allows conflicts to occur. 
Hardware does not check for conflicts.
4.2
IO Address Space
There are 64 KB + 3 bytes of IO space (0h–10002h) for accessing IO registers. Most IO 
registers exists for legacy functions in the PCU or for PCI devices, while some are 
claimed by the Processor Transaction Router for graphics and for the PCI configuration 
space access registers.
Table 34. Fixed Memory Ranges in the Platform Controller Unit (PCU)
Device
Start Address
End Address
Comments
Low BIOS (Flash Boot)
000E0000h
000FFFFFh
Starts 128 KB below 1 MB; Firmware/BIOS
IO APIC
FEC00000h
FEC00040h
Starts 20 MB below 4 GB
HPET
FED00000h
FED003FFh
Starts 19 MB below 4 GB
TPM (LPC)
FFD40000h
FFD40FFFh
Starts 16 KB above HPET range
High BIOS/Boot Vector
FFFF0000h
FFFFFFFFh
Starts 64 KB below 4 GB; Firmware/BIOS