Intel G1620T CM8063701448300 User Manual

536

Datasheet

This register contains a number of fields that provide a specific level of configurability 

for the OUT DMA that is part of Debug Device logic. This configurability is above and 

beyond that defined in the xHCI specification.

Default: 00000000h

7: 0

00h

RW

Max Power Field (MPF): This field will be used by USB Debug Device to report 

maximum power consumption when the device is fully operational. This value is 

returned by bMaxPower field in response to Configuration Descriptor read from the 

debug device. Note: bU1DevExitLat and bU2DevExitLat fields returned in BOS 

Descriptor read will be taken from the corresponding fields from the Host Controller 

space.

Type: Memory Mapped I/O Register

(Size: 32 bits)

MBAR Type: PCI Configuration Register (Size: 32 bits)
MBAR Reference: [B:0, D:20, F:0] + 10h

Power Well: Core

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSV

D

EN_ACK_FCA

RS

VD_1

E

N

_ACK_FIFO_ICA

RS

VD_2

CL_OWN_CS

RET

_

OD_ACK_CR

RS

VD_3

RET

_

O

D

CF_SM_IS

RET_OD

RF_SM_IS

RE

T_ODR

D

F_SM_IS

RS

VD_4

31: 19

0000h

RO

Reserved (RSVD): Reserved.

18

0b

RW

Enable ACK FIFO credit accounting (EN_ACK_FCA): Setting this field will enable 

ACK FIFO credit accounting. ODMA will ensure that ample room exists in the ACK FIFO 

for expected device responses prior to initiating a given DP

17: 14

0h

RO

Reserved (RSVD_1): Reserved.

13

0b

RW

Enable ACK FIFO ICA mechanisms (EN_ACK_FIFO_ICA): Setting this field will 

enable ACK FIFO individual credit accounting mechanisms for Async vs. Periodic 

Endpoints. ODMA will ensure that ample room exists in the ACK FIFO for expected 

device responses prior to initiating a given DP

12: 9

0h

RO

Reserved (RSVD_2): Reserved.

8

0b

RW

Clear ownership of context semaphore (CL_OWN_CS): Setting this field generates 

a pulse that clears the ownership of the context semaphore that is shared between the 

Out DMA Response and Completion Finite State Machines