Intel G1620T CM8063701448300 User Manual

Datasheet

699

There are four lanes and up to four PCI Express root ports, each supporting the PCI 
Express* Base Specification, Rev. 2.0 at a maximum 5 GT/s signaling rate. The root 
ports can be configured to support a diverse set of lane assignments.

See 

 for additional details.

The signal description table has the following headings:

•

Signal Name: The name of the signal/pin

•

Direction: The buffer direction can be either input, output, or I/O (bidirectional)

•

Type: The buffer type found in 

•

Description: A brief explanation of the signal’s function

PMC_WAKE_PCIE[3:0]# are not listed, but can be used by PCI Express* devices. 
Please see 

 for 

details.

IO

  

  

IO

  

  

IO

  

  

IO

  

  

PCI Express* 2.0

RP 1

RP 2

RP 3

RP 4

Lane 0 Lane 1 Lane 2 Lane 3