Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
PCI Express* 2.0
830
Datasheet
17.9.24
PCS_DWORD23 (pcs_dword23)—Offset 5Ch
Access Method
Default: 00180888h
17.9.25
PCS_DWORD24 (pcs_dword24)—Offset 60h
Access Method
Default: 0001C020h
Type: Message Bus Register
(Size: 32 bits)
pcs_dword23: [Port: 0xA6] + (400h + 5Ch)
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
iclk
qcfg_spar
e_7_0
ic
lkicfg_
spare_7
ic
lkicfg_spar
e_6_3
ic
lkicfg_spar
e_2_0
re
se
rv
ed
526
i_drvc
fg_3_0
i_ploadc
fg_3_0
ipbiasc
trl_3_0
Bit
Range
Default &
Access
Description
31:24
0h
RW
iclkqcfg_spare_7_0: (Bonus bits for Data Lane Clk Distrubtion block)
23
0h
RW
iclkicfg_spare_7: Repurposed for IREF backup mode in DL Select bit to enable diode
based IREF in DL 0 - functional mode, use IREFGEN loop output 1 - bypass IREF loop,
use diode connected PMOS output Ensure IREF loop amp is enabled by forcing
reg_ivrefen and ivrefen_ovrd to 1
22:19
3h
RW
iclkicfg_spare_6_3: TX MUX tail current strength setting
18:16
0h
RW
iclkicfg_spare_2_0: CLK Distribution Monitor MUX Select
15:12
0h
RW
reserved526: reserved
11:8
8h
RW
i_drvcfg_3_0: CLK: Driver Tail Current Control
7:4
8h
RW
i_ploadcfg_3_0: CLK: Pbias Ref Current Selection
3:0
8h
RW
ipbiasctrl_3_0: CLK: Pmos-Load Pbias Voltage Control
Type: Message Bus Register
(Size: 32 bits)
pcs_dword24: [Port: 0xA6] + (400h + 60h)
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write