Intel G1620T CM8063701448300 User Manual
Product codes
CM8063701448300
PCU – Power Management Controller (PMC)
964
Datasheet
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
In systems using the APIC, the SCI can be routed to interrupts IRQs[11:9] or
IRQs[23:20]. The interrupt polarity changes depending on whether it is on an interrupt
shareable with a PIRQ or not. The interrupt remains asserted until all SCI sources are
removed.
IRQs[23:20]. The interrupt polarity changes depending on whether it is on an interrupt
shareable with a PIRQ or not. The interrupt remains asserted until all SCI sources are
removed.
shows which events can cause an SMI and SCI. Note that some events can
be programmed to cause either an SMI or SCI. The usage of the event for SCI (instead
of SMI) is typically associated with an ACPI-based system. Each SMI or SCI source has
a corresponding enable and status bit.
of SMI) is typically associated with an ACPI-based system. Each SMI or SCI source has
a corresponding enable and status bit.
Table 142. Causes of SMI and SCI (Sheet 1 of 2)
Event
Status Indication
1
Enable Condition
Interrupt Result
SMI_EN.
GBL_SMI_EN=1b
SMI_EN.
GBL_SMI_EN=0b
PM1_CNT.S
CI_EN=1b
PM1_CNT.S
CI_EN=0b
PM1_CNT.S
CI_EN=1b
PM1_CNT.S
CI_EN=0b
Power Button
Override
3
PM1_STS_EN.
PWRBTNOR_STS
None
SCI
None
SCI
None
RTC Alarm
PM1_STS_EN.
RTC_STS
PM1_STS_EN_EN.
RTC_EN=1b
SCI
SMI
SCI
None
Power Button Press
PM1_STS_EN.
PWRBTN_STS
PM1_STS_EN_EN.
PWRBTN_EN=1b
SCI
SMI
SCI
None
SMI_EN.BIOS_RLS
bit written to 1b
4
PM1_STS_EN.
GBL_STS
PM1_STS_EN_EN.
GBL_EN=1b
SCI
ACPI Timer overflow
(2.34 seconds)
PM1_STS_EN.
TMROF_STS
PM1_STS_EN_EN.
TMROF_EN =1b
SCI
SMI
SCI
None
GPI[n]
9
GPE0a_STS.
CORE_GPIO_STS[n]
2
or
GPE0a_STS.
GPE0a_STS.
SUS_GPIO_STS[n]
2
GPIO_ROUT[n] =
10b &
GPE0a_EN.
GPE0a_EN.
CORE_GPIO_EN[n]
2
=1b
or
GPE0a_EN.
or
GPE0a_EN.
SUS_GPIO_EN[n]
2
=
1b
SCI
None
SCI
None
Internal, Bus 0,
PME-Capable Agents
(PME_B0)
GPE0a_STS.
PME_B0_STS
GPE0_EN.
PME_B0_EN=1b
SCI
SMI
SCI
None
BATLOW# pin goes
low
GPE0a_STS.
BATLOW_STS#
GPE0_EN.
BATLOW_EN=1b
SCI
SMI
SCI
None
PCI Express GPE
messages
GPE0a_STS.
HOT_PLUG_STS
GPE0_EN.
HOT_PLUG_EN=1b
SCI
None
SCI
None
Software Generated
GPE
GPE0a_STS.
SWGPE_STS
GPE0_EN.
SWGPE_EN=1b
SCI
SMI
SCI
None
PCI Express Hot
Plug SCI Message
GPE0a_STS.
HOT_PLUG_STS
GPE0_EN.
HOT_PLUG_EN=1b
SCI
None
SCI
None