Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
100
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.1.12 MH_CHN_ASTN
MEMHOT Domain Channel Association.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x118
Bit
Attr
Default
Description
31:22
RW_LV
0x0
MH1_IO_CNTR (mh1_io_cntr):
MEM_HOT[1:0]# Input Output Counter in number of CNTR_500_NANOSEC. 
When MH_IO_CNTR is zero, the counter is loaded with MH_SENSE_PERIOD 
in the next CNTR_500_NANOSEC. When count is greater than 
MH_IN_SENSE_ASSERT, the MEM_HOT[1:0]# output driver may be turn on 
if the corresponding MEM_HOT# event is asserted. The receiver is turned 
off during this time. When count is equal or less than 
MH_IN_SENSE_ASSERT, MEM_HOT[1:0]# output is disabled and receiver is 
turned on. Hardware will decrement this counter by 1 every time 
CNTR_500_NANOSEC is decremented to zero. When the counter is zero, 
the next CNFG_500_NANOSEC count is loaded with 
MH_IN_SENSE_ASSERT. This counter is subject to PMSI pause (at 
quiencense) and resume (at wipe).
21:12
RW_LV
0x0
MH0_IO_CNTR (mh0_io_cntr):
MEM_HOT[1:0]# Input Output Counter in number of CNTR_500_NANOSEC. 
When MH_IO_CNTR is zero, the counter is loaded with MH_SENSE_PERIOD 
in the next CNTR_500_NANOSEC. When count is greater than 
MH_IN_SENSE_ASSERT, the MEM_HOT[1:0]# output driver may be turn on 
if the corresponding MEM_HOT# event is asserted. The receiver is turned 
off during this time. When count is equal or less than 
MH_IN_SENSE_ASSERT, MEM_HOT[1:0]# output is disabled and receiver is 
turned on. BIOS calculate number of CNTR_500_NANOSEC hardware will 
decrement this register by 1 every CNTR_500_NANOSEC. When the counter 
is zero, the next CNTR_500_NANOSEC count is loaded with 
MH_IN_SENSE_ASSERT. This counter is subject to PMSI pause (at 
quiencense) and resume (at wipe). 
11:10
RV
-
Reserved.
9:0
RW_LV
0x0
CNTR_500_NANOSEC (cntr_500_nanosec):
500ns base counters used for the MEM_HOT counters and the SMBus 
counters. BIOS calculate number of DCLK to be equivalent to 500 
nanoseconds. CNTR_500_NANOSEC hardware will decrement this register 
by 1 every CNTR_500_NANOSEC. When the counter is zero, the next 
CNTR_500_NANOSEC count is loaded with CNFG_500_NANOSEC. This 
counter is subject to PMSI pause (at quiencense) and resume (at wipe). 
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x11c
Bit
Attr
Default
Description
31:24
RV
-
Reserved.
23:20
RO
0xb
MH1_2ND_CHN_ASTN (mh1_2nd_chn_astn):
MemHot[1]# 2nd Channel Association bit 23: is valid bit. Note: Valid bit 
means the association is valid and it does not implies the channel is 
populated.
bit 22-20: 2nd channel ID within this MEMHOT domain.
Note: This register is hardcoded in design. It is read-accessible by firmware.
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