Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
101
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.1.13 MH_TEMP_STAT
MEMHOT TEMP Status.
19:16
RO
0xa
MH1_1ST_CHN_ASTN (mh1_1st_chn_astn):
MemHot[1]# 1st Channel Association bit 19: is valid bit. Note: Valid bit 
means the association is valid and it does not implies the channel is 
populated.
bit 18-16: 1st channel ID within this MEMHOT domain
Note: This register is hardcoded in design. It is read-accessible by firmware. 
Design must make sure this register is not removed by downstream tools.
15:8
RV
-
Reserved.
7:4
RO
0x9
MH0_2ND_CHN_ASTN (mh0_2nd_chn_astn):
MemHot[0]# 2nd Channel Association bit 7: is valid bit. Note: Valid bit 
means the association is valid and it does not implies the channel is 
populated.
bit 6-4: 2nd channel ID within this MEMHOT domain
Note: This register is hardcoded in design. It is read-accessible by firmware. 
Design must make sure this register is not removed by downstream tools.
3:0
RO
0x8
MH0_1ST_CHN_ASTN (mh0_1st_chn_astn):
MemHot[0]# 1st Channel Association bit 3: is valid bit. Note: Valid bit 
means the association is valid and it does not implies the channel is 
populated or exist.
bit 2-0: 1st channel ID within this MEMHOT domain
Note: This register is hardcoded in design. It is read-accessible by firmware. 
Design must make sure this register is not removed by downstream tools.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x11c
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x120
Bit
Attr
Default
Description
31:31
RW_V
0x0
MH1_DIMM_VAL (mh1_dimm_val):
Valid if set. PCU microcode search the hottest DIMM temperature and write 
the hottest temperature and the corresponding Hottest DIMM CID/ID and 
set the valid bit. MEMHOT hardware logic process the corresponding 
MEMHOT data when there is a MEMHOT event. Upon processing, the valid 
bit is reset. PCU microcode can write over existing valid temperature since a 
valid temperature may not occur during a MEMHOT event. If PCU microcode 
set the valid bit occur at the same cycle that the MEMHOT logic processing 
and try to clear, the PCU microcode set will dominate since it is a new 
temperature is updated while processing logic tries to clear an existing 
temperature.
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