Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
105
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.1.16 SMBCMD_[0:1]
A write to this register initiates a DIMM EEPROM access through the SMBus/I2C.
27:24
RO_V
0x7
Last Issued TSOD Slave Address (tsod_sa):
This field captures the last issued TSOD slave address. Here is the slave 
address and the DDR CHN and DIMM slot mapping:
Slave Address: 0 -- Channel: Even Chn; Slot #: 0
Slave Address: 1 -- Channel: Even Chn; Slot #: 1
Slave Address: 2 -- Channel: Even Chn; Slot #: 2
Slave Address: 3 -- Channel: Even Chn; Slot #: 3 (reserved)
Slave Address: 4 -- Channel: Odd Chn; Slot #: 0
Slave Address: 5 -- Channel: Odd Chn; Slot #: 1
Slave Address: 6 -- Channel: Odd Chn; Slot #: 2
Slave Address: 7 -- Channel: Odd Chn; Slot #: 3 (reserved)
A value of 0x8 in this register indicates to poll MXB temperature rather than 
a DIMM temperature, values above 0x8 are invalid.
A value of 0x3 and 0x7 (reserved) in this fields can be used as an indication 
that the FSM has not yet started.
Since this field only captures the TSOD polling slave address. During SMB 
error handling, software should check the hung SMB_TSOD_POLL_EN state 
before disabling the SMB_TSOD_POLL_EN in order to qualify whether this 
field is valid.
23:16
RV
-
Reserved.
15:0
RO_V
0x0
SMB_RDATA (smb_rdata):
Read DataHolds data read from SMBus Read commands.
Since TSOD/EEPROM are I2C* devices and the byte order is MSByte first in 
a word read, reading of I2C using word read should return 
SMB_RDATA[15:8] = I2C_MSB and SMB_RDATA[7:0] = I2C_LSB. If reading 
of I2C using byte read, the SMB_RDATA[15:8] = don’t care; 
SMB_RDATA[7:0] = read_byte.
If we have a SMB slave connected on the bus, reading of the SMBus slave 
using word read should return SMB_RDATA[15:8] = SMB_LSB and 
SMB_RDATA[7:0] = SMB_MSB.
If the software is not sure whether the target is I2C or SMBus slave, use 
byte access.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x180, 0x190
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x184, 0x194
Bit
Attr
Default
Description
31:31
RW_V
0x0
SMB_CMD_TRIGGER (smb_cmd_trigger):
CMD trigger: After setting this bit to 1, the SMBus master will issue the SMBus 
command using the other fields written in SMBCMD_[0:1] and SMBCntl_[0:1]. 
Note: the '-V' in the attribute implies the hardware will reset this bit when the 
SMBus command is being started.
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