Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
107
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x188, 0x198
Bit
Attr
Default
Description
31:28
RWS
0xa
SMB_DTI (smb_dti):
Device Type Identifier: This field specifies the device type identifier. Only 
devices with this device-type will respond to commands.
'0011' specifies TSOD.
'1010' specifies EEPROM's.
'0110' specifies a write-protect operation for an EEPROM.
Other identifiers can be specified to target non-EEPROM devices on the SMBus.
Note: IMC based hardware TSOD polling uses hardcoded DTI. Changing this 
field has no effect on the hardware based TSOD polling.
27:27
RWS_V
0x1
SMB_CKOVRD (smb_ckovrd):
Clock Override
'0'  Clock signal is driven low, overriding writing a '1' to CMD.
'1'  Clock signal is released high, allowing normal operation of CMD.
Toggling this bit can be used to 'budge' the port out of a 'stuck' state.
Software can write this bit to 0 and the SMB_SOFT_RST to 1 to force hung 
SMBus controller and the SMB slaves to idle state without using power good 
reset or warm reset.
Note: software need to set the SMB_CKOVRD back to 1 after 35ms in order to 
force slave devices to timeout in case there is any pending transaction. The 
corresponding SMB_STAT_x.SMB_SBE error status bit may be set if there was 
such pending transaction timeout (ungraceful termination). If the pending 
transaction was a write operation, the slave device content may be corrupted 
by this clock override operation. A subsequent SMB command will automatically 
cleared the SMB_SBE.
iMC added SMBus timeout control timer in B0. When the timeout control timer 
expired, the SMBCKOVRD# will "deassert", i.e. return to 1 value.
26:26
RW_LB
0x1
SMB_DIS_WRT (smb_dis_wrt):
Disable SMBus Write
Writing a '0' to this bit enables CMD to be set to 1; Writing a 1 to force CMD bit 
to be always 0, i.e. disabling SMBus write. This bit can only be written in 
SMMode. SMBus Read is not affected. I2C Write Pointer Update Command is not 
affected.
Important Note to BIOS: Since BIOS is the source to update SMBCNTL_x 
register initially after reset, it is important to determine whether the SMBus can 
have write capability before writing any upper bits (bit24-31) via byte-enable 
config write (or writing any bit within this register via 32b config write) within 
the SMBCNTL register.
25:11
RV
-
Reserved1:
 Reserved.
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