Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
108
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.1.18 SMB_TSOD_POLL_RATE_CNTR_[0:1]
10:10
RW
0x0
SMB_SOFT_RST (smb_soft_rst):
SMBus software reset strobe to graceful terminate pending transaction (after 
ACK) and keep the SMB from issuing any transaction until this bit is cleared. If 
slave device is hung, software can write this bit to 1 and the SMB_CKOVRD to 0 
(for more than 35ms)to force hung the SMB slaves to timeout and put it in idle 
state without using power good reset or warm reset.
Note: software need to set the SMB_CKOVRD back to 1 after 35ms in order to 
force slave devices to timeout in case there is any pending transaction. The 
corresponding SMB_STAT_x.SMB_SBE error status bit may be set if there was 
such pending transaction timeout (ungraceful termination). If the pending 
transaction was a write operation, the slave device content may be corrupted 
by this clock override operation. A subsequent SMB command will automatically 
cleared the SMB_SBE.
 If the IMC HW perform SMB timeout with the SMB_SBE_EN = 1. Software 
should simply clear the SMB_SBE and SMB_SOFT_RST sequentially after 
writing the SMB_CKOVRD = 0 and SMB_SOFT_RST = 1 asserting clock override 
and perform graceful txn termination. Hardware will automatically deassert the 
SMB_CKOVRD update to 1 after the preconfigured 35ms/65ms timeout.
9:9
RV
-
Reserved.
8:8
RW_LB
0x0
SMB_TSOD_POLL_EN (smb_tsod_poll_en):
TSOD polling enable
'0': disable TSOD polling and enable SPDCMD accesses.
'1': disable SPDCMD access and enable TSOD polling.
It is important to make sure no pending SMBus transaction and the TSOD 
polling must be disabled (and pending TSOD polling must be drained) before 
changing the TSOD_POLL_EN.
7:0
RW_LB
0x0
TSOD_PRESENT for the lower and upper channels (tsod_present):
DIMM slot mask to indicate whether the DIMM is equipped with TSOD sensor.
Bit 7: must be programmed to zero. Upper channel slot #3 is not supported
Bit 6: TSOD PRESENT at upper channel (ch 1 or ch 3) slot #2
Bit 5: TSOD PRESENT at upper channel (ch 1 or ch 3) slot #1
Bit 4: TSOD PRESENT at upper channel (ch 1 or ch 3) slot #0
Bit 3: must be programmed to zero. Lower channel slot #3 is not supported
Bit 2: TSOD PRESENT at lower channel (ch 0 or ch 2) slot #2
Bit 1: TSOD PRESENT at lower channel (ch 0 or ch 2) slot #1
Bit 0: TSOD PRESENT at lower channel (ch 0 or ch 2) slot #0
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x18c, 0x19c
Bit
Attr
Default
Description
31:18 RV
-
Reserved.
17:0
RW_LV
0x0
SMB_TSOD_POLL_RATE_CNTR (smb_tsod_poll_rate_cntr):
TSOD poll rate counter. When it is decremented to zero, reset to zero or written 
to zero, SMB_TSOD_POLL_RATE value is loaded into this counter and appear 
the updated value in the next DCLK. 
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x188, 0x198
Bit
Attr
Default
Description
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