Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
109
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.1.19 SMB_PERIOD_CFG
SMBus Clock Period Config. 
13.2.1.20 SMB_PERIOD_CNTR
SMBus Clock Period Counter. 
13.2.1.21 SMB_TSOD_POLL_RATE
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x1a0
Bit
Attr
Default
Description
31:16
RV
-
Reserved1:
Reserved
15:0
RWS
0xfa0
SMB_CLK_PRD (smb_clk_prd):
This field specifies both SMBus Clock in number of DCLK. Note: In order to 
generate a 50% duty cycle SCL, half of the SMB_CLK_PRD is used to generate 
SCL high. SCL must stay low for at least another half of the SMB_CLK_PRD 
before pulling high. It is recommend to program an even value in this field 
since the hardware is simply doing a right shift for the divided by 2 operation.
For presilicon validation, minimum 8 can be set to speed up the simulation.
Note the 100 KHz SMB_CLK_PRD default value is calculated based on 800 MTs 
(400 MHz) DCLK.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x1a4
Bit
Attr
Default
Description
31:16
RO_V
0x0
SMB1_CLK_PRD_CNTR (smb1_clk_prd_cntr):
SMBus #1 Clock Period Counter for Ch 23. This field is the current SMBus Clock 
Period Counter Value. 
15:0
RO_V
0x0
SMB0_CLK_PRD_CNTR (smb0_clk_prd_cntr):
SMBus #0 Clock Period Counter for Ch 01. This field is the current SMBus Clock 
Period Counter Value. 
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x1a8
Bit
Attr
Default
Description
31:18 RV
-
Reserved.
17:0
RWS
0x3e800
SMB_TSOD_POLL_RATE (smb_tsod_poll_rate):
TSOD poll rate configuration between consecutive TSOD accesses to the TSOD 
devices on the same SMBus segment. This field specifies the TSOD poll rate in 
number of 500 ns per CNFG_500_NANOSEC register field definition.For 
presilicon validation, minimum TBD can be set (along with the 
CNFG_500_NANOSEC set to 8) to speed up the simulation.
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