Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
119
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.2.13 LEAKY_BUCKET_CNTR_HI
13.2.3
Device 15, 29 Functions 2-5
The Device 15 and 29 Function 2-5 contain Target Address Decode, Channels Rank and 
Memory Timing registers. The registers in Device 29 Functions 2 to 5 are identical to 
those in Device 15 Functions 2 to 5, respectively. The Device 15 Function 2, 3, 4 and 5 
registers address iMC 0 Channel 0, 1, 2 and 3, while the Device 29 Function 2, 3, 4 and 
5 registers address iMC 1 Channel 0, 1, 2 and 3. 
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
1
Bus:
1
Device: 29
Function:
1
Offset:
0xc4
Bit
Attr
Default
Description
31:10
RV
-
Reserved.
9:0
RW_V
0x0
Leaky Bucket Counter High Limit (leaky_bkt_cntr_hi):
This is the upper 10-bit of the leaky bucket counter. The full counter is actually 
a 53b “DCLK” counter. There is a least significant 11b of the 53b counter is not 
captured in CSR. The carry “strobe” from the not-shown least significant 11b 
counter will trigger this 42b counter pair to count. The 42b counter-pair is 
compared with the two-hot encoding threshold specified by the 
LEAKY_BUCKET_CFG_HI and LEAKY_BUCKET_CFG_LO pair. When the counter 
bits specified by the LEAKY_BUCKET_CFG_HI and LEAKY_BUCKET_CFG_LO are 
both set, the 53b counter is reset and the leaky bucket logic will generate a 
LEAK strobe last for 1 DCLK.
Register name
Offset
Size
VID
0x0
16
DID
0x2
16
PCICMD
0x4
16
PCISTS
0x6
16
RID
0x8
8
CCR
0x9
24
CLSR
0xc
8
PLAT
0xd
8
HDR
0xe
8
BIST
0xf
8
SVID
0x2c
16
SDID
0x2e
16
CAPPTR
0x34
8
INTL
0x3c
8
INTPIN
0x3d
8
MINGNT
0x3e
8
MAXLAT
0x3f
8
PXPCAP
0x40
32
DIMMMTR_0
0x80
32
DIMMMTR_1
0x84
32
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