Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
121
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
19:16
RW_LB
0x0
RANK_DISABLE control (rank_disable):
RANK Disable Control to disable patrol, refresh and ZQCAL operation. This 
bit setting must be set consistently with TERM_RNK_MSK, i.e. both 
corresponding bits cannot be set at the same time. In the other word, a 
disabled rank must not be selected for the termination rank.
RANK_DISABLE[3], i.e. bit 19: rank 3 disable. Note 
DIMMMTR_2.RANKDISABLE[3] is don't care since DIMM 2 must not be 
quad-rank
RANK_DISABLE[2], i.e. bit 18: rank 2 disable. Note 
DIMMMTR_2.RANKDISABLE[2] is don't care since DIMM 2 must not be 
quad-rank
RANK_DISABLE[1], i.e. bit 17: rank 1 disable
RANK_DISABLE[0], i.e. bit 16: rank 0 disable
when set, no patrol or refresh will be perform on this rank. ODT termination 
is not affected by this bit.
15:15
RV
-
Reserved.
14:14
RW_LB
0x0
DIMM_POP (dimm_pop):
In VMSE 2:1 mode:
This DIMM_POP field reports the real DIMM population. DIMM populated if 
set; otherwise, unpopulated. If none of the fields from DIMMMTR 0/1/2 is 
set, DDRIO DLL will not be enabled.
In VMSE 1:1 mode:
When populates DIMMs in the two Lock-step Channel DIMM slots, only one 
of the DIMM_POP will be set to 1, the other DIMM_POP will still be 0. 
13:12
RW_LB
0x0
RANK_CNT (rank_cnt):
00 - SR
01 - DR
10 - QR
11 - reserved
11:9
RV
-
Reserved.
8:7
RW_LB
0x0
DDR3_WIDTH (ddr3_width):
00 - x4
01 - x8
10 - x16
11 - reserved
Used to determine if a configuration is capable of supporting DDDC.
6:5
RV
-
Reserved.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
2,3,4,5
Bus:
1
Device: 29
Function:
2,3,4,5
Offset:
0x80, 0x84, 0x88
Bit
Attr
Default
Description
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