Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
126
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.4.2
PMONCNTR_[0:4]
This register is a perfmon counter. Software can both read it and write it.
13.2.4.3
PMONCNTR_FIXED
This register is a perfmon counter. Software can both read it and write it.
19:16
RO
0x1
Capability Version (capability_version):
PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
Note:
This capability structure is not compliant with Versions beyond 1.0, since they 
require additional capability registers to be reserved. The only purpose for this 
capability structure is to make enhanced configuration space available. 
Minimizing the size of this structure is accomplished by reporting version 1.0 
compliancy and reporting that this is an integrated root port device. As such, 
only three Dwords of configuration space are required for this structure.
15:8
RO
0x0
Next Capability Pointer (next_ptr):
Pointer to the next capability. Set to 0 to indicate there are no more capability 
structures.
7:0
RO
0x10
Capability ID (capability_id):
Provides the PCI Express capability ID assigned by PCI-SIG.
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0x40
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0xa0, 0xa8, 0xb0, 0xb8 , 0xc0
Bit
Attr
Default
Description
63:48
RV
-
Reserved.
47:0
RW_V
0x0
Counter Value (countervalue):
This is the current value of the counter.
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0xd0
Bit
Attr
Default
Description
63:48
RV
-
Reserved.
47:0
RW_V
0x0
Counter Value (countervalue):
This is the current value of the counter.
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