Intel E7-8891 v2 CM8063601377422 User Manual
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
Perfmon Counter Control Register
, 0xdc, 0xe0, 0xe4, 0xe8
This field is compared directly against an incoming event value for events
that can increment by 1 or more in a given cycle. Since the widest event
from the UnCore is 7bits (queue occupancy), bit 31 is unused. The result of
the comparison is effectively a 1 bit wide event, i.e., the counter will be
incremented by 1 when the comparison is true (the type of comparison
depends on the setting of the 'invert' bit - see bit 23 below) no matter how
wide the original event was. When this field is zero, threshold comparison is
disabled and the event is passed without modification.
This bit indicates how the threshold field will be compared to the incoming
event. When 0, the comparison that will be done is threshold >= event.
When set to 1, the comparison that will be done is inverted from the case
where this bit is set to 0, i.e., threshold < event. The invert bit only works
when Threshold != 0. So, if one would like to invert a non-occupancy event
(like LLC Hit), one needs to set the threshold to 1.
Counter Enable (counterenable):
This field is the local enable for the PerfMon Counter. This bit must be
asserted in order for the PerfMon counter to begin counting the events
selected by the ‘event select’, and ‘unit mask’ bits see the fields below.
There is one bit per PerfMon Counter. Note that if this bit is set to 1 but the
Unit Control Registers have determined that counting is disabled, then the
counter will not count.
Overflow Enable (overflowenable):
Setting this bit will enable the counter to send an overflow signal. If this bit
is not set, the counter will wrap around when it overflows without triggering
anything. If this bit is set and the Unit's configuration register has Overflow
enabled, then a signal will be transmitted to the Ubox.
Edge Detect (edgedetect):
Edge Detect allows one to count either 0 to 1 or 1 to 0 transitions of a given
event. For example, we have an event that counts the number of cycles in
L0s mode in Intel
QPI. By using edge detect, one can count the number of
times that we entered L0s mode (by detecting the rising edge).
Edge detect only works in conjunction with thresholding. This is true even
for events that can only increment by 1 in a given cycle (like the L0s
example above). In this case, one should set a threshold of 1. One can also
use Edge Detect with queue occupancy events. For example, if one wanted
to count the number of times when the TOR occupancy was larger than 5,
one would select the TOR occupancy event with a threshold of 5 and set the
Edge Detect bit.
Edge detect can also be used with the invert. This is generally not
particularly useful, as the count of falling edges compared to rising edges
will always on differ by 1.