Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
137
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.4.18 TCRWP
Timing Constraints DDR3 Read Write Parameter. 
15:12
RW
0x6
T_WTR (t_wtr):
DCLK delay from start of internal write transaction to internal read command 
(must be at least the larger value of 4 DCLK or 7.5ns)
iMC's Write to Read Same Rank (T_WRSR) is automatically calculated based 
from TCDBP.T_CWL + 4 + T_WTR.
For LRDIMM running in rank multiplication mode, iMC will continue to use the 
above equation for T_WRSR even if the WRITE and READ are targeting same 
logical rank but at different physical ranks behind the LRDIMM buffer, In the 
other word, iMC will not be able to dynamically switch to TWRDR timing. In 
order to avoid timing violation in this scenario, BIOS must configure the TWTR 
parameter to be the MAX (T_WTR of LRDIMM, (T_WRDR' - TCL + 2)). Note: 
Due to the lighter electrical loading behind the LRDIMM buffer, further 
optimization can be tuned during post-silicon to reduce the T_WRDR' 
parameter instead of directly using the TCRWP.T_WRDR parameter.
11:8
RW
0x3
T_CKE (t_cke):
CKE minimum pulse width (must be at least the larger value of 3 DCLK or 5ns)
7:4
RW
0xa
T_RTP (t_rtp):
Internal READ Command to PRECHARGE Command delay, (must be at least the 
larger value of 4 DCLK or 7.5ns)
3:3
RV
-
Reserved1:
Reserved.
2:0
RW
0x5
T_RRD (t_rrd):
ACTIVE to ACTIVE command period, (must be at least the larger value of 4 
DCLK or 6ns)
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device:
30Function:0,1,4,5
Offset:
0x204
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0x208
Bit
Attr
Default
Description
31:30
RW
0x0
T_WRDR_UPPER (t_wrdr_upper):
Upper 2 bits (Bits 4:3) of t_wrdr field.
29:27
RW
0x0
T_CCD (t_ccd):
back to back READ to READ or CAS to CAS from same rank separation 
parameter.The actual JEDEC CAS to CAS command separation is (T_CCD + 
4) DCLKs measured between the clock assertion edges of the two 
corresponding asserted command CS#.
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