Intel E7-8891 v2 CM8063601377422 User Manual
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
Timing Constraints DDR3 Read Write Parameter.
DCLK delay from start of internal write transaction to internal read command
(must be at least the larger value of 4 DCLK or 7.5ns)
iMC's Write to Read Same Rank (T_WRSR) is automatically calculated based
from TCDBP.T_CWL + 4 + T_WTR.
For LRDIMM running in rank multiplication mode, iMC will continue to use the
above equation for T_WRSR even if the WRITE and READ are targeting same
logical rank but at different physical ranks behind the LRDIMM buffer, In the
other word, iMC will not be able to dynamically switch to TWRDR timing. In
order to avoid timing violation in this scenario, BIOS must configure the TWTR
parameter to be the MAX (T_WTR of LRDIMM, (T_WRDR' - TCL + 2)). Note:
Due to the lighter electrical loading behind the LRDIMM buffer, further
optimization can be tuned during post-silicon to reduce the T_WRDR'
parameter instead of directly using the TCRWP.T_WRDR parameter.
CKE minimum pulse width (must be at least the larger value of 3 DCLK or 5ns)
Internal READ Command to PRECHARGE Command delay, (must be at least the
larger value of 4 DCLK or 7.5ns)
ACTIVE to ACTIVE command period, (must be at least the larger value of 4
DCLK or 6ns)
Upper 2 bits (Bits 4:3) of t_wrdr field.
back to back READ to READ or CAS to CAS from same rank separation
parameter.The actual JEDEC CAS to CAS command separation is (T_CCD +
4) DCLKs measured between the clock assertion edges of the two
corresponding asserted command CS#.