Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
140
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.4.20 TCRFP
Timing Constraints DDR3 Refresh Parameter. 
13.2.4.21 TCRFTP
Timing Constraints Refresh Timing Parameter. 
10:8
RW
0x0
T_CWL_ADJ (t_cwl_adj):
This register defines additional WR data delay per channel in order to overcome 
the WR-flyby issue.
The total CAS write latency that the DDR sees is the sum of T_CWL and the 
T_CWL_ADJ.
000 - no added latency  (default)
001 - 1 Dclk of added latency
010 - 2 Dclk of added latency
011 - 3 Dclk of added latency
1xx - Reduced latency by 1 Dclk. Not supported at tCWL = 5
7:5
RW
0x3
T_XP (t_xp):
Exit Power Down with DLL on to any valid command; Exit Precharge Power 
Down with DLL frozen to commands not requiring a locked DLL.
4:0
RW
0xa
T_XPDLL (t_xpdll):
Exit Precharge Power Down with DLL frozen to commands requiring a locked 
DLL.
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0x20c
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0x210
Bit
Attr
Default
Description
31:16
RV
-
Reserved.
15:12
RW
0x9
REF_PANIC_WM (ref_panic_wm):
tREFI count level in which the refresh priority is panic (default is 9)
It is recommended to set the panic WM at least to 9, in order to utilize the 
maximum no-refresh period possible
11:8
RW
0x8
REF_HI_WM (ref_hi_wm):
tREFI count level that turns the refresh priority to high (default is 8)
7:0
RW
0x3f
OREFNI (orefni):
Rank idle period that defines an opportunity for refresh, in DCLK cycles
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