Intel E7-8891 v2 CM8063601377422 User Manual

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

141

Datasheet Volume Two: Functional Description, February 2014

Timing Constraints Self-Refresh Timing Parameter. 

31:25

RW

0x9

T_REFIX9 (t_refix9):

period of min between 9 * T_REFI and tRAS maximum (normally 70 micro-sec) 

in 1024 * DCLK cycles.The default value will need to reduce 100 DCLK cycles - 

uncertainty on timing of panic refresh

24:15

RW

0x80

T_RFC (t_rfc):

Time of refresh - from beginning of refresh until next ACT or refresh is allowed 

(in DCLK cycles)

Here are the recommended T_RFC for 2Gb DDR3:
0800 MT/s : 040h
1067 MT/s : 056h
1333 MT/s : 06Bh
1600 MT/s : 080h
1867 MT/s : 096h

14:0

RW

0x62c

T_REFI (t_refi):

Defines the average period between refreshes in DCLK cycles. This register 

defines the upper 15b of the 16b tREFI counter limit. The least significant bit of 

the counter limit is always zero.

Here are the recommended T_REFI[14:0] setting for 7.8 micro-sec:
0800 MT/s : 0C30h
1067 MT/s : 1040h
1333 MT/s : 1450h
1600 MT/s : 1860h
1867 MT/s : 1C70h

31:27

RW

0xc

T_MOD (t_mod):

Mode Register Set command update delay.

26:26

RV

-

Reserved.

25:16

RW

0x100

T_ZQOPER (t_zqoper):

Normal operation Full calibration time

15:12

RW

0xb

T_XSOFFSET (t_xsoffset):

tXS = T_RFC + 10ns. Setup of T_XSOFFSET is # of cycles for 10 ns. Range 

is between 3 and 11 DCLK cycles