Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
146
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.4.30 RDIMMTIMINGCNTL2
28:16
RW
0x12c0
T_STAB (t_stab):
Stabilizing time in number of DCLK, i.e. the DCLK must be stable for T_STAB 
before any access to the device take place. We have included tCKSRX in the 
T_STAB programming since processor does not have separate tCKSRX 
parameter control to delay self-refresh exit latency from clock stopped 
conditions.
Note #1: zero value in T_STAB is reserved and it is important to AVOID 
programming a zero value in the T_STAB.
Recommended settings Note: contains stretch goal and/or over-clock 
frequency examples:
FREQ 
TSTAB for RDIMM (including tCKSRX value)
0800 
0960h + 5h = 0965h
1067 
0C80h + 5h = 0c85h
1333 
0FA0h + 7h = 0FA7h
1600 
12C0h + 8h = 12C8h
1867 
15E0h + Ah = 15EAh
2133 
1900h + Bh651 = 190Bh
FREQ 
TSTAB for UDIMM (i.e. tCKSRX value)
0800 7h
1067 7h
1333 9h
1600 Ah
1867 Ch
2133 Dh 
15:4
RV
-
Reserved.
3:0
RW
0x8
T_MRD (t_mrd):
Command word to command word programming delay in DCLK
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0x240
Bit
Attr
Default
Description
31:4
RV
-
Reserved1:
Reserved.
3:0
RW
0x5
T_CKOFF (t_ckoff):
tCKOFF timing parameter:
Number of tCK required for both DCKE0 and DCKE1 to remain LOW before both 
CK/CK# are driven Low
Minimum setting is 2.
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0x23c
Bit
Attr
Default
Description
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