Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
154
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.5.12 LEAKY_BKT_2ND_CNTR_REG
13.2.5.13 DEVTAG_CNTL_[0:7]
SDDC Usage model. 
When the number of correctable errors (CORRERRCNT_x) from a particular rank 
exceeds the corresponding threshold (CORRERRTHRSHLD_y), hardware will generate a 
SMI interrupt and preserve the failing device in the FailDevice field. SMM software will 
read the failing device on the particular rank. Software then set the EN bit to enable 
substitution of the failing device/rank with the parity from the rest of the devices inline. 
For independent channel configuration, each rank can tag once. Up to 8 ranks can 
be tagged. 
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
2,3,6,7
Bus:
1
Device: 30
Function:
2,3,6,7
Offset:
0x138
Bit
Attr
Default
Description
31:16
RW
0x0
LEAKY_BKT_2ND_CNTR_LIMIT (leaky_bkt_2nd_cntr_limit):
Secondary Leaky Bucket Counter Limit (2b per DIMM). This register defines 
secondary leaky bucket counter limit for all 8 logical ranks within channel. 
The counter logic will generate the secondary LEAK pulse to decrement the 
rank's correctable error counter by 1 when the corresponding rank leaky 
bucket rank counter roll over at the predefined counter limit. The counter 
increment at the primary leak pulse from the LEAKY_BUCKET_CNTR_LO and 
LEAKY_BUCKET_CNTR_HI logic.
Bit[31:30]: Rank 7 Secondary Leaky Bucket Counter Limit
Bit[29:28]: Rank 6 Secondary Leaky Bucket Counter Limit
Bit[27:26]: Rank 5 Secondary Leaky Bucket Counter Limit
Bit[25:24]: Rank 4 Secondary Leaky Bucket Counter Limit
Bit[23:22]: Rank 3 Secondary Leaky Bucket Counter Limit
Bit[21:20]: Rank 2 Secondary Leaky Bucket Counter Limit
Bit[19:18]: Rank 1 Secondary Leaky Bucket Counter Limit
Bit[17:16]: Rank 0 Secondary Leaky Bucket Counter Limit
The value of the limit is defined as the following:
00b: 4x Primary leak strobe (four times the value programmed by the 
LEAKY_BKT_CFG_HI and LEAKY_BKT_CFG_LO).
01b: 1x Primary leak strobe (the value programmed by the 
LEAKY_BKT_CFG_HI and LEAKY_BKT_CFG_LO).
10b: 2x Primary leak strobe (two times the value programmed by the 
LEAKY_BKT_CFG_HI and LEAKY_BKT_CFG_LO).
11b: 3x Primary leak strobe (three times the value programmed by the 
LEAKY_BKT_CFG_HI and LEAKY_BKT_CFG_LO).
15:0
RW_V
0x0
LEAKY_BKT_2ND_CNTR (leaky_bkt_2nd_cntr):
Per rank secondary leaky bucket counter (2b per rank)
bit [15:14]: rank 7 secondary leaky bucket counter
bit [13:12]: rank 6 secondary leaky bucket counter
bit [11:10]: rank 5 secondary leaky bucket counter
bit [9:8]: rank 4 secondary leaky bucket counter
bit [7:6]: rank 3 secondary leaky bucket counter
bit [5:4]: rank 2 secondary leaky bucket counter
bit [3:2]: rank 1 secondary leaky bucket counter
bit [1:0]: rank 0 secondary leaky bucket counter
downloadlike
ArtboardArtboardArtboard
Report Bug