Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
186
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13:13
RO_FW
0x0
DISABLE_RDIMM:
RDIMM disable control. When set, RDIMM support is disabled by disabling the 
RDIMM control word access. In addition, the upper 5 bits of the 13b_T_STAB 
register will be treated as zeros, i.e. the T_STAB can only have max of 255 
DCLK delay after clock-stopped power down mode which is in sufficient for 
normal RDIMM clock stabilization; hence, users will not be able to support self-
refresh with clock off mode (S3, pkg C6) if the RDIMM disable is blown to one.
12:12
RO_FW
0x0
DISABLE_3N:
3N disable control. When set, 3N mode under normal/IOSAV operation 
(excluding MRS) is disabled
11:11
RO_FW
0x0
DISABLE_DIR:
DIR disable control. When set, directory is disabled. 
10:10
RO_FW
0x0
DISABLE_ECC:
ECC disable control. When set, ECC is disabled. 
9:9
RO_FW
0x0
DISABLE_QR_DIMM:
QR DIMM disable control. When set, CS signals for QR-DIMM in slot 0-1 is 
disabled. Note: some CS may have multiplexed with address signal to support 
extended addressing. The CS signal disabling is only applicable to CS not the 
being multiplexed with address
8:8
RO_FW
0x0
DISABLE_4GBIT_DDR3:
4 Gb disable control. When set, the address decode to the corresponding 4 Gb 
mapping is disabled. 
Note: LR-DIMM’s logical device density is also limited to 4 Gb when this is set. 
7:7
RO_FW
0x0
DISABLE_8GBIT_DDR3:
8 Gb or higher disable control. When set, the address decode to the 
corresponding 8 Gb or higher mapping is disabled. Note: LR-DIMM’s logical 
device density is also limited to 8 Gb when this is set. 
6:6
RV
-
Reserved.
5:5
RO_FW
0x0
DISABLE_3_DPC:
3 DPC disable control. When set, CS signals for DIMM slot 2 are disabled. Note: 
some CS may have multiplexed with address signal to support extended 
addressing. The CS signal disabling is only applicable to CS not the being 
multiplexed with address. 
4:4
RO_FW
0x0
DISABLE_2_DPC:
2 DPC disable control. When set, CS signals for DIMM slot 1-2 (i.e. slots 0 is not 
disabled) are disabled. 
Note: some CS may have multiplexed with address signal to support extended 
addressing. The CS signal disabling is only applicable to CS not the being 
multiplexed with address
3:0
RO_FW
0x0
CHN_DISABLE:
channel disable control. When set, the corresponding channel is disabled. 
Type:
CFG
PortID: N/A
Bus:
1
Device: 10
Function:
3
Offset:
0x90
Bit
Attr
Default
Description
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