Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
199
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
11:11
RW1C
0x0
sta:
Signaled Target Abort
This bit is set when a root port signals a completer abort completion status 
on the primary side (internal bus of uncore). This condition includes a PCI 
Express port forwarding a completer abort status received on a completion 
from the secondary.
Hardware will not set this bit while in DMI mode.
10:9
RO
0x0
devsel_timing:
Not applicable. Hardwired to 0.
8:8
RW1C
0x0
mdpe:
Master Data Parity Error
This bit is set by a root port if the Parity Error Response bit in the PCI 
Command register is set and it either receives a completion with poisoned 
data from the primary side or it forwards a packet with data (including MSI 
writes) to the primary side with poison.
Hardware will not set this bit while in DMI mode.
7:7
RO
0x0
fast_back_to_back:
Not applicable to PCI Express. Hardwired to 0.
6:6
RV
-
Reserved. 
5:5
RO
0x0
pci66mhz_capable:
Not applicable to PCI Express. Hardwired to 0.
4:4
RO
0x1
capabilities_list:
This bit indicates the presence of a capabilities list structure.
3:3
RO_V
0x0
intx_status:
This Read-only bit reflects the state of the interrupt in the PCI Express Root 
Port. Only when the Interrupt Disable bit in the command register is a 0 and 
this Interrupt Status bit is a 1, will this device generate INTx interrupt. 
Setting the Interrupt Disable bit to a 1 has no effect on the state of this 
bit.This bit does not get set for interrupts forwarded to the root port from 
downstream devices in the hierarchy. When MSI are enabled, Interrupt 
status should not be set.
Hardware will not set this bit while in DMI mode.
2:0
RV
-
Reserved. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x6
Bit
Attr
Default
Description
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