Intel E7-8891 v2 CM8063601377422 User Manual

206

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

Memory Limit Register.

Prefetchable Memory Base Register.

15:4

RW

0x0

memory_limit_address:

Corresponds to A[31:20] of the 32 bit memory window’s limit address that 

corresponds to the upper limit of the range of memory accesses that will be 

passed by the PCI Express bridge.The Memory Base and Memory Limit 

registers define a memory mapped I/O nonprefetchable address range (32-

bit addresses) and the IIO directs accesses in this range to the PCI Express 

port based on the following formula:

MEMORY_BASE <= A[31:20] <= MEMORY_LIMIT

The upper 12 bits of both the Memory Base and Memory Limit registers are 

read / write and corresponds to the upper 12 address bits, A[31:20] of 32-bit 

addresses. Thus, the bottom of the defined memory address range will be 

aligned to a 1 MB boundary and the top of the defined memory address range 

will be one less than a 1 MB boundary.

Notes:
Setting the memory limit less than memory base disables the 32-bit memory 

range altogether.
Note that in general the memory base and limit registers won’t be 

programmed by software without clearing the MSE bit first.

3:0

RV

-

Reserved. 

15:4

RW

0xfff

prefetchable_memory_base_address:

Corresponds to A[31:20] of the prefetchable memory address range’s base 

address of the PCI Express port. See also the PLIMU register description.

3:0

RO

0x1

prefetchable_memory_base_address_capability:

IIO sets this bit to 01h to indicate 64bit capability.