Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
210
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
4:4
RW
0x0
vga16b:
This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of 
VGA I/O address precluding the decoding of alias addresses every 1 KB.
0: execute 10-bit address decodes on VGA I/O accesses.
1: execute 16-bit address decodes on VGA I/O accesses.
Notes:
This bit only has meaning if bit 3 of this register is also set to 1, enabling VGA 
I/O decoding and forwarding by the bridge.
Refer to PCI-PCI Bridge Specification Revision 1.2 for further details of this bit 
behavior.
3:3
RW
0x0
vgaen:
Controls the routing of CPU initiated transactions targeting VGA compatible 
I/O and memory address ranges. This bit must only be set for one p2p port in 
the entire system.
2:2
RW
0x0
isaen:
Modifies the response by the root port to an I/O access issued by the core 
that target ISA I/O addresses. This applies only to I/O addresses that are 
enabled by the IOBASE and IOLIM registers.
1: The root port will not forward to PCI Express any I/O transactions 
addressing the last 768 bytes in each 1KB block even if the addresses are 
within the range defined by the IOBASE and IOLIM registers.
0: All addresses defined by the IOBASE and IOLIM for core issued I/O 
transactions will be mapped to PCI Express.
1:1
RW
0x0
serre:
SERR Response Enable
This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL 
messages from the PCI Express port to the primary side.
1: Enables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL 
messages.
0: Disables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
0:0
RW
0x0
perre:
Parity Error Response Enable  
This only effect this bit has is on the setting of bit 8 in the SECSTS register
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x3e
Bit
Attr
Default
Description
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