Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
214
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.35 MSGADR
The MSI Address Register (MSIAR) contains the system specific address information to 
route MSI interrupts from the root ports and is broken into its constituent fields.
6:4
RW
0x0
mme:
Multiple Message Enable.
Applicable only to PCI Express ports. Software writes to this field to indicate 
the number of allocated messages which is aligned to a power of two. When 
MSI is enabled, the software will allocate at least one message to the device. 
A value of 000 indicates 1 message. Any value greater than or equal to 001 
indicates a message of 2.
See MSIDR for discussion on how the interrupts are distributed amongst the 
various sources of interrupt based on the number of messages allocated by 
software for the PCI Express ports.
3:1
RO
0x1
mmc:
Multiple Message Capable.
Intel Xeon processor E7-2800/4800/8800 v2 product family Product Family’s 
Express ports support two messages for all their internal events.
0:0
RW
0x0
msien:
Software sets this bit to select INTx style interrupt or MSI interrupt for root 
port generated interrupts.
0: INTx interrupt mechanism is used for root port interrupts, provided the 
override bits in MISCCTRLSTS allow it
1: MSI interrupt mechanism is used for root port interrupts, provided the 
override bits in MISCCTRLSTS allow it
Note there bits 4:2 and bit 2 MISCCTRLSTS can disable both MSI and INTx 
interrupt from being generated on root port interrupt events.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x62
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x64
Bit
Attr
Default
Description
31:2
RW
0x0
address_id:
Refer to the Interrupt Chapter for details of how this field is interpreted by 
IIO hardware. The definition of this field depends on whether interrupt 
remapping is enabled or disabled.
1:0
RV
-
Reserved. 
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