Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
216
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.39 PXPCAPID
PCI Express Capability Identity
14.2.40 PXPNXTPTR
PCI Express Next Pointer.
14.2.41 PXPCAP
PCI Express Capabilities Register.
1:0
RO_V
0x0
pending_bits:
Relevant only when MSI is enabled and used for interrupts generated by the 
root port. When MSI is not enabled or used by the root port, this register 
always reads a value 0. For each Pending bit that is set, the PCI Express port 
has a pending associated message. When only one message is allocated to 
the root port by software, only pending bit 0 is set /cleared by hardware and 
pending bit 1 always reads 0.
Hardware sets this bit whenever it has an interrupt pending to be sent. This 
bit remains set till either the interrupt is sent by hardware or the status bits 
associated with the interrupt condition are cleared by software.
Refer to the RAS/PM chapters for details of how this bit is set and cleared.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x70
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x90
Bit
Attr
Default
Description
7:0
RO
0x10
capability_id:
Provides the PCI Express capability ID assigned by PCI-SIG.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x91
Bit
Attr
Default
Description
7:0
RO
0xe0
next_ptr:
This field is set to the PCI PM capability.
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