Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
217
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x92
Bit
Attr
Default
Description
15:14
RV
-
Reserved. 
13:9
RO
0x0
interrupt_message_number:
Applies to root ports. This field indicates the interrupt message number that 
is generated for PM/Hot Plug/BW-change events. When there are more than 
one MSI interrupt Number allocated for the root port MSI interrupts, this 
register field is required to contain the offset between the base Message 
Data and the MSI Message that is generated when there are PM/Hot 
Plug/BW-change interrupts. IIO assigns the first vector for PM/Hot Plug/BW-
change events and so this field is set to 0.
8:8
RW_O
0x0
slot_implemented:
Applies only to the root ports.
1: indicates that the PCI Express link associated with the port is connected 
to a slot.
0: indicates no slot is connected to this port.
Notes:
This register bit is of type “write once” and is set by BIOS.
7:4
RO_V
0x4
device_port_type:
This field identifies the type of device. It is set to 0x4 for all the Express 
ports.
3:0
RW_O
0x2
capability_version:
This field identifies the version of the PCI Express capability structure, which 
is 2h as of now. This register field is left as RW_O to cover any unknowns 
with Gen3.
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