Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
223
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14:12
RW_O
0x3
l0s_exit_latency:
This field indicates the L0s exit latency (i.e L0s to L0) for the 
PCI Express* port.
000: Less than 64 ns
001: 64 ns to less than 128 ns
010: 128 ns to less than 256 ns
011: 256 ns to less than 512 ns
100: 512 ns to less than 1 us
101: 1 is to less than 2 us
110: 2 is to 4 us
111: More than 4 us
This register is made writable once by BIOS so that the value is settable 
based on experiments post-si.
11:10
RW_O
0x2
active_state_link_pm_support:
This field indicates the level of active state power management 
supported on the given PCI Express* port.
00: Disabled
01: L0s Entry Supported
10: L1 Entry Supported.
11: L0s and L1 Supported
9:4
RW_O
0x4
maximum_link_width:
This field indicates the maximum width of the given PCI Express Link 
attached to the port.
000001: x1
000010: x2
000100: x4
001000: x8
010000: x16
Others: Reserved
This is left as a RW_O register for bios to update based on the platform 
usage of the links.
3:0
RW_O
0x3
maxlnkspd:
This field indicates the maximum link speed of this Port.
The encoding is the binary value of the bit location in the Supported Link 
Speeds Vector in LNKCAP2 that corresponds to the maximum link speed.
Intel Xeon processor E7-2800/4800/8800 v2 product family Product 
Family supports a maximum of 8Gbps.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x9c
Bit
Attr
Default
Description
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