Intel E7-8891 v2 CM8063601377422 User Manual

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

225

Datasheet Volume Two: Functional Description, February 2014

5:5

WO

0x0

retrain_link:

A write of 1 to this bit initiates link retraining in the given PCI 

Express/DMI port by directing the LTSSM to the recovery state if 

the current state is [L0, L0s or L1]. If the current state is anything 

other than L0, L0s, L1 then a write to this bit does nothing. This bit 

always returns 0 when read.It is permitted to write 1b to this bit 

while simultaneously writing modified values to other fields in this 

register. If the LTSSM is not already in Recovery or Configuration, 

the resulting Link training must use the modified values. If the 

LTSSM is already in Recovery or Configuration, the modified values 

are not required to affect the Link training that’s already in 

progress.

4:4

RW

0x0

link_disable:

This field controls whether the link associated with the PCI 

Express/DMI port is enabled or disabled. When this bit is a 1, a 

previously configured link would return to the ’disabled’ state as 

defined in the PCI Express Base Specification, Revision 2.0. When 

this bit is clear, an LTSSM in the ’disabled’ state goes back to the 

detect state.
0: Enables the link associated with the PCI Express port
1: Disables the link associated with the PCI Express port

3:3

RO

0x0

read_completion_boundary:

Set to zero to indicate IIO could return read completions at 64B 

boundaries

1:0

RW_V (Function 0)
RW (Function 1-3)

0x0

active_state_link_pm_control:

When 01b or 11b, L0s on transmitter is enabled, otherwise it is 

disabled. 10 and 11 enables L1 ASPM.