Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
227
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.48 SLTCAP
PCI Express Slot Capabilities 
The Slot Capabilities register identifies the PCI Express specific slot capabilities.
11:11
RO_V
0x0
link_training:
This field indicates the status of an ongoing link training session in the PCI 
Express port
0: LTSSM has exited the recovery/configuration state.
1: LTSSM is in recovery/configuration state or the Retrain Link was set but 
training has not yet begun.
The IIO hardware clears this bit once LTSSM has exited the 
recovery/configuration state. Refer to PCI Express Base Specification, 
Revision 2.0 for details of which states within the LTSSM would set this bit 
and which states would clear this bit.
10:10
RV
-
Reserved. 
9:4
RO_V
0x0
negotiated_link_width:
This field indicates the negotiated width of the given PCI Express link after 
training is completed. 
Only x1, x2, x4, x8 and x16 link width negotiations are possible in the 
processor for Device#2-3 and only x1, x2 and x4 on Device#0. 
A value of 0x01 in this field corresponds to a link width of x1, 0x02 indicates 
a link width of x2 and so on, with a value of 0x10 for a link width of x16.The 
value in this field is reserved and could show any value when the link is not 
up. Software determines if the link is up or not by reading bit 13 of this 
register.
3:0
RO_V
0x1
current_link_speed:
This field indicates the negotiated link speed of the given PCI Express Link.
0001: 2.5Gbps
0010: 5Gbps (This value will not be set in Port 0 if the DMIGEN2EN strap is 
‘0’)
0011: 8Gbps (Port 0 does not support this speed, and processor will never 
set this value when Gen3_OFF fuse is blown)
Others: Reserved.
The value in this field is not defined when the link is not up. Software 
determines if the link is up or not by reading bit[13] of this register.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (DMI2 Mode)
Offset:
0x1b2
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xa2
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xa4
Bit
Attr
Default
Description
31:19
RW_O
0x0
physical_slot_number:
This field indicates the physical slot number of the slot connected to the PCI 
Express port and is initialized by BIOS.
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