Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
228
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
18:18
RO
0x0
command_complete_not_capable:
Intel Xeon processor E7-2800/4800/8800 v2 product family Product Family 
is capable of command complete interrupt.
17:17
RW_O
0x0
electromechanical_interlock_present:
This bit when set indicates that an Electromechanical Interlock is 
implemented on the chassis for this slot and that lock is controlled by bit 11 
in Slot Control register. This field is initialized by BIOS based on the system 
architecture.BIOS note: this capability is not set if the Electromechanical 
Interlock control is connected to main slot power control.
This is expected to be used only for Express Module hotpluggable slots.
16:15
RW_O
0x0
slot_power_limit_scale:
This field specifies the scale used for the Slot Power Limit Value and is 
initialized by BIOS. IIO uses this field when it sends a Set_Slot_Power_Limit 
message on PCI Express.Range of Values: 00: 1.0x 01: 0.1x 10: 0.01x 11: 
0.001x Writes to this register trigger a Set_Slot_Power_Limit message to be 
sent. 
14:7
RW_O
0x0
slot_power_limit_value:
This field specifies the upper limit on power supplied by slot in conjunction 
with the Slot Power Limit Scale value defined previously Power limit (in 
Watts) = SPLS x SPLV. This field is initialized by BIOS. IIO uses this field 
when it sends a Set_Slot_Power_Limit message on PCI Express. Writes to 
this register trigger a Set_Slot_Power_Limit message to be sent. Design 
Note: IIO sends the Set_Slot_Power_Limit message on the link at first link 
up condition (except on the DMI link operating in DMI mode) without 
regards to whether this register and the Slot Power Limit Scale register are 
programmed yet by BIOS. 
6:6
RW_O
0x0
hot_plug_capable:
This field defines hot-plug support capabilities for the PCI Express port.
0: indicates that this slot is not capable of supporting Hot-plug operations.
1: indicates that this slot is capable of supporting Hot-plug operations
This bit is programmed by BIOS based on the system design. This bit must 
be programmed by bios to be consistent with the VPP enable bit for the port.
5:5
RW_O
0x0
hot_plug_surprise:
This field indicates that a device in this slot may be removed from the 
system without prior notification. This field is initialized by BIOS.
0: indicates that hot-plug surprise is not supported
1: indicates that hot-plug surprise is supported
Generally this bit is not expected to be set because the only know usage 
case for this is the ExpressCard FF. But that is not really expected usage in 
Intel Xeon processor E7-2800/4800/8800 v2 product family Product Family 
context. But this bit is present regardless to allow a usage if it arises.
This bit is used by IIO hardware to determine if a transition from DL_active 
to DL_Inactive is to be treated as a surprise down error or not. If a port is 
associated with a hotpluggable slot and the hotplug surprise bit is set, then 
any transition to DL_Inactive is not considered an error. Refer to PCI Express 
Base Specification, Revision 2.0 for further details.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xa4
Bit
Attr
Default
Description
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