Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
230
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.49 SLTCON
PCI Express Slot Control.
Any write to this register will set the Command Completed bit in the SLTSTS register, 
ONLY if the VPP enable bit for the port is set. If the port’s VPP enable bit is set (that is, 
hotplug for that slot is enabled), then the required actions on VPP are completed before 
the Command Completed bit is set in the SLTSTS register. If the VPP enable bit for the 
port is clear, then the write simply updates this register see individual bit definitions for 
details but the Command Completed bit in the SLTSTS register is not set.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xa8
Bit
Attr
Default
Description
15:13
RV
-
Reserved. 
12:12
RWS
0x0
data_link_layer_state_changed_enable:
When set to 1, this field enables software notification when Data Link Layer 
Link Active bit in the LNKSTS register changes state
11:11
RW
0x0
electromechanical_interlock_control:
When software writes either a 1 to this bit, IIO pulses the EMIL pin per PCI 
Express Server/Workstation Module Electromechanical Spec Rev 1.0. Write of 
0 has no effect. This bit always returns a 0 when read. If electromechanical 
lock is not implemented, then either a write of 1 or 0 to this register has no 
effect.
10:10
RWS
0x1
power_controller_control:
If a power controller is implemented, when writes to this field will set the 
power state of the slot per the defined encodings. Reads of this field must 
reflect the value from the latest write, even if the corresponding hot-plug 
command is not executed yet at the VPP, unless software issues a write 
without waiting for the previous command to complete in which case the 
read value is undefined.
0: Power On
1: Power Off
Note: If the link experiences an unexpected DL_Down condition that is not 
the result of a Hot Plug removal, the processor follows the PCI Express 
specification for logging Surprise Link Down. SW is required to set 
SLTCON[10] to 0 (Power On) in all devices that do not connect to a slot that 
supports Hot-Plug to enable logging of this error in that device.
For devices connected to slots supporting Hot-Plug operations, SLTCON[10] 
usage to control PWREN# assertion is as described elsewhere.
9:8
RW
0x3
power_indicator_control:
If a Power Indicator is implemented, writes to this field will set the Power 
Indicator to the written state. Reads of this field must reflect the value from 
the latest write, even if the corresponding hot-plug command is not executed 
yet at the VPP, unless software issues a write without waiting for the previous 
command to complete in which case the read value is undefined.
00: Reserved.
01: On
10: Blink (IIO drives 1 Hz square wave for Chassis mounted LEDs)
11: Off
IIO does not generated the Power_Indicator_On/Off/Blink messages on PCI 
Express when this field is written to by software.
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