Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
233
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.51 ROOTCON
PCI Express Root Control.
5:5
RO_V
0x0
mrl_sensor_state:
This bit reports the status of an MRL sensor if it is implemented.
0: MRL Closed
1: MRL Open
Refer to RAS Chapter for details of how this bit is shifted in on the VPP bit 
stream.
4:4
RW1C
0x0
command_completed:
This bit is set by IIO when the hot-plug command has completed and the 
hot-plug controller is ready to accept a subsequent command. It is 
subsequently cleared by software after the field has been read and 
processed. This bit provides no guarantee that the action corresponding to 
the command is complete.Any write to SLTCON (regardless of the port is 
capable or enabled for hot-plug) is considered a 'hot-plug' command.
If the port is not hot-plug capable or hot-plug enabled, then the hot-plug 
command does not trigger any action on the VPP port but the command is 
still completed via this bit.
3:3
RW1C
0x0
presence_detect_changed:
This bit is set by IIO when the value reported in bit 6 is changes. It is 
subsequently cleared by software after the field has been read and 
processed.
2:2
RW1C
0x0
mrl_sensor_changed:
This bit is set if the value reported in bit 5 changes. It is subsequently 
cleared by software after the field has been read and processed.
1:1
RW1C
0x0
power_fault_detected:
This bit is set by IIO when a power fault event is detected by the power 
controller (which is reported via the VPP bit stream). It is subsequently 
cleared by software after the field has been read and processed.Refer to RAS 
Chapter for details of how this bit is shifted in on the VPP bit stream.
0:0
RW1C
0x0
attention_button_pressed:
This bit is set by IIO when the attention button is pressed. It is subsequently 
cleared by software after the field has been read and processed.Refer to RAS 
Chapter for details of how this bit is shifted in on the VPP bit stream.
IIO silently discards the Attention_Button_Pressed message if received from 
PCI Express link without updating this bit.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xaa
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xac
Bit
Attr
Default
Description
15:5
RV
-
Reserved.
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