Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
234
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
4:4
RW
0x0
crsswvisen:
CRS software visibility Enable
This bit, when set, enables the Root Port to return Configuration 
Request Retry Status (CRS) Completion Status to software.
3:3
RW
RW_L (Device 3 
Function 0 only
0x0
pmeinten:
This field controls the generation of MSI interrupts/INTx interrupts 
for PME messages.
1: Enables interrupt generation upon receipt of a PME message
0: Disables interrupt generation for PME messages
2:2
RW
0x0
sefeen:
System Error on Fatal Error Enable  
This field enables notifying the internal IIO core error logic of 
occurrence of an uncorrectable fatal error at the port or below its 
hierarchy. The internal core error logic of IIO then decides if/how to 
escalate the error further (pins/message etc).
1: indicates that an internal IIO core error logic notification should 
be generated if a fatal error (ERR_FATAL) is reported by any of the 
devices in the hierarchy associated with and including this port.
0: No internal IIO core error logic notification should be generated 
on a fatal error (ERR_FATAL) reported by any of the devices in the 
hierarchy associated with and including this port.
Note that generation of system notification on a PCI Express fatal 
error is orthogonal to generation of an MSI/INTx interrupt for the 
same error. Both a system error and MSI/INTx can be generated on 
a fatal error or software can chose one of the two.
Refer to PCI Express Base Specification, Revision 2.0 for details of 
how this bit is used in conjunction with other error control bits to 
generate core logic notification of error events in a PCI Express port.
Note that since this register is defined only in PCIe* mode for 
Device#0, this bit will read a 0 in DMI mode. So, to enable core 
error logic notification on DMI mode fatal errors, BIOS must set bit 
35 of MISCCTRLSTS to a 1 (to override this bit) on Device#0 in DMI 
mode.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xac
Bit
Attr
Default
Description
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