Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
250
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.67 APICBASE
ACPI Base Register.
14.2.68 APICLIMIT
ACPI Limit Register.
0:0
RW_L (Device 2 and 3 
Function 0)
RW (Device 0 Function 0, 
Device 2 and 3 Function 1-3)
0x0
v:
Applies only to root ports. When set, the component 
validates the Bus Number from the Requester ID of 
upstream Requests against the secondary subordinate 
Bus Numbers.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x116
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x140
Bit
Attr
Default
Description
15:12
RV
-
Reserved.
11:1
RW
0x0
addr:
Bits 31:20 are assumed to be 0xFECh. Bits 8:0 are a don’t care for address 
decode. Address decoding to the APIC range is done as 
APICBASE.ADDR[31:8] <= A[31:8] <= APICLIMIT.ADDR[31:8].
Outbound accesses to the APIC range are claimed by the root port and 
forwarded to PCIe, if bit 0 is set, even if the MSE bit of the root port is clear or 
the root port itself is in D3hot state.
0:0
RW
0x0
en:
enables the decode of the APIC window
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x142
Bit
Attr
Default
Description
15:12
RV
-
Reserved.
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