Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
251
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.69 VSECPHDR
PCI Express Enhanced Capability Header - DMI2 Mode.
14.2.70 VSHDR
Vendor Specific Header - DMI2 Mode.
11:1
RW
0x0
addr:
Applies only to root ports.
Bits 31:20 are assumed to be 0xFECh. Bits 8:0 are a don’t care for address 
decode. Address decoding to the APIC range is done as 
APICBASE.ADDR[31:8] <= A[31:8] <= APICLIMIT.ADDR[31:8].
Outbound accesses to the APIC range are claimed by the root port and 
forwarded to PCIe, if the range is enabled, even if the MSE bit of the root port 
is clear or the root port itself is in D3hot state.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x142
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (DMI2 Mode)
Offset:
0x144
Bit
Attr
Default
Description
31:20
RO
0x1d0
next_capability_offset:
This field points to the next Capability in extended configuration space or is 0 
if it is that last capability. 
19:16
RO
0x1
capability_version:
Set to 1h for this version of the PCI Express logic
15:0
RO
0xb
pci_express_extended_cap_id:
Assigned for Vendor Specific Capability
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (DMI2 Mode)
Offset:
0x148
Bit
Attr
Default
Description
31:20
RO
0x3c
vsec_length:
This field points to the next Capability in extended configuration space which 
is the ACS capability at 150h.
19:16
RO
0x1
vsec_version:
Set to 1h for this version of the PCI Express logic
15:0
RO
0x4
vsec_id:
Identifies Intel Vendor Specific Capability for AER on DMI
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