Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
261
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.84 MISCCTRLSTS_0
MISC Control and Status Register 0.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x188
Bit
Attr
Default
Description
31:31
RW
0x0
disable_l0s_on_transmitter:
When set, IIO never puts its tx in L0s state, even if OS 
enables it via the Link Control register.
30:30
RW_O
0x1
inbound_io_disable:
29:29
RW
0x1
cfg_to_en:
Disables/enables config timeouts, independently of other 
timeouts.
28:28
RW
0x0
to_dis:
Disables timeouts completely. 
27:27
RWS
0x0
system_interrupt_only_on_link_bw_management_status:
This bit, when set, will disable generating MSI and Intx 
interrupts on link bandwidth (speed and/or width) and 
management changes, even if MSI or INTx is enabled that 
is, will disable generating MSI or INTx when LNKSTS bits 15 
and 14 are set. Whether or not this condition results in a 
system event like SMI/PMI/CPEI is dependent on whether 
this event masked or not in the XPCORERRMSK register.
26:26
RW_LV (Device 2 and 3 
Function 0)
RW (Device 0 Function 0, 
Device 2 and 3 Function 1-
3)
0x0
eoifd:
EOI Forwarding Disable - Disable EOI broadcast to this 
PCIe* link  
When set, EOI message will not be broadcast down this 
PCIe* link. When clear, the port is a valid target for EOI 
broadcast.
25:25
RV
-
Reserved.
24:24
RW
0x0
peer2peer_memory_read_disable:
When set, peer-to-peer memory reads are master aborted 
otherwise they are allowed to progress per the peer-to-peer 
decoding rules.
23:23
RW
0x0
phold_disable:
Applies only to Dev#0When set, the IIO responds with 
Unsupported request on receiving assert_phold message 
from ICH and results in generating a fatal error.
22:22
RWS
0x0
check_cpl_tc:
21:21
RW_O
0x0
zero_ob_tc:
Forces the TC field to zero for outbound requests.
1: TC is forced to zero on all outbound transactions 
regardless of the source TC value
0: TC is not altered
Note:
In DMI mode, TC is always forced to zero and this bit has 
no effect.
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