Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
265
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.86 PCIE_IOU_BIF_CTRL
PCIe* Port Bifurcation Control.
1:1
RW
0x0
override_system_error_on_pcie_correctable_error_enable:
When set, correctable errors on PCI Express (that have been successfully 
propagated to the primary interface of the port) are sent to the IIO core 
error logic (for further escalation) regardless of the setting of the equivalent 
bit in the ROOTCTRL register. When clear, the correctable errors are only 
propagated to the IIO core error logic if the equivalent bit in ROOTCTRL 
register is set.
For Dev#0 in DMI mode and Dev#3/Fn#0, unless this bit is set, DMI link 
related correctable errors will never be notified to system software.
0:0
RW
0x0
acpi_pme_inten:
When set, Assert/Deassert_PMEGPE messages are enabled to be generated 
when ACPI mode is enabled for handling PME messages from PCI Express. 
See Power Management Chapter for more details of this bit’s usage. When 
this bit is cleared (from a 1), a Deassert_PMEGPE message is scheduled on 
behalf of the root port if an Assert_PMEGPE message was sent last from the 
root port.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x18c
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0
Bus:
0
Device:
3Function:0
Offset:
0x190
Bit
Attr
Default
Description
15:4
RV
-
Reserved.
3:3
WO
0x0
iou_start_bifurcation:
When software writes a 1 to this bit, IIO starts the port 0 
bifurcation process. After writing to this bit, software can poll 
the Data Link Layer link active bit in the LNKSTS register to 
determine if a port is up and running. Once a port bifurcation 
has been initiated by writing a 1 to this bit, software cannot 
initiate any more write-1 to this bit (write of 0 is ok).
Notes:
That this bit can be written to a 1 in the same write that 
changes values for bits 2:0 in this register and in that case, the 
new value from the write to bits 2:0 take effect.
This bit always reads a 0b.
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