Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
266
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.87 DMICTRL
2:0
RWS
RO (Device 0 
Function 0)
0x4
0x0 (Device 0 
Function 0)
iou_bifurcation_control:
To select a IOU bifurcation, software sets this field and then 
either
a) sets bit 3 in this register to initiate training OR
b) resets the entire Intel Xeon processor E7-2800/4800/8800 
v2 product family Product Family and on exit from that reset,
CPU will bifurcate the ports per the setting in this field.
For Device 2 and Device 3 Function 0:
000: x4x4x4x4 (operate lanes 15:12 as x4, 11:8 as x4, 7:4 as 
x4 and 3:0 as x4)
001: x4x4x8 (operate lanes 15:12 as x4, 11:8 as x4 and 7:0 as 
x8)
010: x8x4x4 (operate lanes 15:8 as x8, 7:4 as x4 and 3:0 as 
x4)
011: x8x8 (operate lanes 15:8 as x8, 7:0 as x8)
100: x16
others: Reserved
For Device 0 Function 0, read only.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (DMI2 Mode)
Offset:
0x1a0
Bit
Attr
Default
Description
63:2
RO
0x0
rsvd:
1:1
RW
0x1
auto_complete_pm:
This bit, if set, enables the DMI port to automatically complete PM message 
handshakes by generating an Ack_Sx or Rst_Warn_Ack message down DMI 
for the following DMI messages received:
Go_S0
Go_S1_RW
Go_S1_Temp
Go_S1_Final
Go_S3
Go_S4
Go_S5
Rst_Warn
Notes:
This is used by PCU microcode to indicate periods of time when it is not ready 
to accept messages and there is a risk the messages will be lost.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0
Bus:
0
Device:
3Function:0
Offset:
0x190
Bit
Attr
Default
Description
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