Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
27
Datasheet Volume Two: Functional Description, February 2014
The Processor Architecture Overview
• Home Snoop Protocol Support: The Home Agent implements Intel QPI v1.1 
“home snoop protocol” by initiating snoops on behalf of the requestor. The HA also 
offers Opportunistic Snoop Broadcast to further optimize performance. 
• Directory Mode Support: The HA only operates in the directory mode. 
2.2.6
Integrated Memory Controller (iMC)
The internal memory controller provides the interface to DDR3 DIMMs via Intel
®
 
Scalable Memory Interconnect (Intel
®
 SMI) 2 and Intel
®
 C102/C104 Scalable Memory 
Buffer expansion silicon. The memory controller communicates to the rest of the 
processor through the Home Agent. Key features are as follows:
• Supports two Intel SMI2 interfaces per memory controller
• One Intel C102/C104 Scalable Memory Buffer per Intel SMI2 interface, with up to 
two DDR3 channels Intel C102/C104 Scalable Memory Buffer
• Up to 3 DDR3 DIMMs on each DDR channel 
• Support up to 8 ranks per channel
• Support 1067, 1333, 1600 MT/s DDR3 frequencies.
• Support 2 GB, 4 GB and 8 GB DRAM technologies
• Support “Corrupt Data Containment” and “MCA Recovery”
• Support memory power management features, that is, CLTT and 
MEM_HOT_C{01/23}_N
2.2.7
Power Control Unit (PCU)
The processor implements a power control unit acting as a core/uncore power and 
thermal manager. It runs its firmware on an internal micro-controller and coordinates 
the socket for its power states.
The PCU algorithmically governs the P-states of the processor, C-states of the core and 
the package C-states of the socket. It also enables the core to go to a higher 
performance state (Intel
®
 Turbo Boost Technology) when the proper set of conditions 
are met.  Conversely, the PCU could throttle the processor to a lower performance state 
when thermal violation occurrs. 
Through specific events, the OS and the PCU will either promote or demote the C-state 
of each core by altering the voltage and frequency.  The system power state (S-state) 
of all the sockets in the system is managed by an external device such as PCH or BMC 
in coordination with all socket PCUs.
The OS and BIOS communicates to the PCU via standardized MSR registers and ACPI. 
The PCU acts as the interface to external management controllers (BMC) via PECI and 
voltage regulators.
2.2.8
Integrated I/O module (IIO)
The I/O module provides features traditionally supported through chipset components. 
One of the benefits is that a server does not require auxiliary chipset components aside 
from the legacy southbridge. The Integrated I/O module provides the following 
features:
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