Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
285
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x288
Bit
Attr
Default
Description
31:31
RW1CS
0x0
LER_Status:
Indicates that an error was detected that caused the PCIe* port to go into a 
live error recovery (LER) mode. While in LER mode, the link goes into a 
LinkDown “Disabled” state and all outbound transactions are aborted 
(including packets that may have caused the error).
This bit cannot be cleared until all the associated unmasked status bits are 
cleared. or the corresponding LER mask bits are set. Once the unmasked 
error condition are cleared, then this bit may be cleared by software writing 
a ‘1’. The link will retrain into LinkUp state and outbound transactions will no 
longer be aborted. Also, inbound transactions will also no longer be blocked.
A link that is forced into a LinkDown “Disabled” state due to LER does not 
trigger a “surprise LinkDown” error in the UNCERRSTS register.
It should be noted that many PCIe* cards will go into internal reset when 
they receive training sequences that indicate the “Disabled” state.
30:30
ROS_V
0x0
LER_Port_Quesced:
Indicates when the port has no more pending inbound or outbound packets 
after the port has entered LER mode. It is used by software to determine 
when it is safe to clear the LER_Status bit to bring the port out of LER 
mode.
29:4
RV
-
Reserved:
3:3
RWS
0x0
LER_INTEN: 
If set, causes an INTx or MSI interrupt from the root port (if enabled in the 
root port) to be generated when LER_Status is set.
2:2
RWS
0x0
LER_Drop_TXN: 
If set, after entering LER subsequent transactions will be dropped as soon 
as the port configuration allows.
1:1
RWS
0x0
LER_Severity_En: 
If set, forces the errors that trigger LER mode to be signaled as a 
correctable error of Severity 0. If cleared, then errors are signaled as 
Uncorrectable Nonfatal Severity 1 or Uncorrectable Fatal Severity 2 as 
specified for the given error.
0:0
RWS
0x0
LER_Enable: 
When set, allows the LER_Status to assert on error. When the status bit is 
set, the port is in LER mode. When this bit is cleared, the LER_Status bit 
can no longer be set on an error.
Note: If this bit is cleared when the LER_Status bit is already set, then 
clearing this bit does not clear the status bit and does not exit LER mode. To 
exit LER mode, the Status bit must be cleared by software.
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