Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
289
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.119 XPPMCL[0:1]
XP PM Compare Low Bits
The value of PMD is compared to the value of PMC. If PMD is greater than PMC, this 
status is reflected in the PERFCON register and/or on the GE[3:0] (TBD) as selected in 
the Event Status Output field of the PMR register.
14.2.120 XPPMDH
XP PM Data High Bits
This register contains the high nibbles from each of the PMD 36-bit counter register.
14.2.121 XPPMCH
XP PM Compare High Bits
This register contains the high nibbles from each of the PMC 36-bit compare registers.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0
Bus:
0
Device:
3Function:0
Offset:
0x488, 0x48c
Bit
Attr
Default
Description
31:0
RW_V
0xffffffff
pm_compare_low_value:
PM compare low value  
Low order bits [31:0] for PM compare register [1:0]. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0
Bus:
0
Device:
3Function:0
Offset:
0x490
Bit
Attr
Default
Description
15:12
RV
-
Reserved.
11:8
RW_V
0x0
high_nibble_pex_counter1_value:
High Nibble PEX Counter1 value  
High order bits [35:32] of the 36-bit PM Data1 register. 
7:4
RV
-
Reserved.
3:0
RW_V
0x0
high_nibble_pex_counter0_value:
High Nibble PEX Counter0 value  
High order bits [35:32] of the 36-bit PM Data0 register. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0
Bus:
0
Device:
3Function:0
Offset:
0x492
Bit
Attr
Default
Description
15:12
RV
-
Reserved.
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