Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
293
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.123 XPPMEVL[0:1]
XP PM Events Low
Selections in this register correspond to fields within the PCIe* header. Each field 
selection is logically combined according to the match equation. The qualifications for 
fields in this register are listed below. It should be noted that the bit selections are 
generic for packet and for either inbound or outbound direction. Because of this, there 
will be bit fields that do not make sense. For these packet matching situations the user 
should select “Either” which acts as a don’t care for the match equation
PCIe* PerfMon Match Equation
PMEV Match  = ((IO_Cfg_Write_event  +  IO_Cfg_Read_event _+ Mem_Write_event  +  
Mem_Read_event + Trusted_write_event + Trusted_read_event + General_event) & 
INOUTBND) + GESEL
4:3
RW
0x0
cto:
PerfMon Trigger Output  
This field selects what the signal is communicated to the chip’s event logic 
structure.
00: No cluster trigger output from PerfMons or header match.
01: PM Status.
10: PM Event Detection.
11: Reserved 
2:2
RW1C
0x0
compare_status:
Compare Status  
This status bit captures a count compare event. The Compare Status field can 
be programmed to allow this bit to be driven to Global Event (GE[3:0]) signals 
which will then distribute the event to the debug logic.
0: no event
1: count compare - PMD counter greater than PMC register when in compare 
mode.
This bit remains set once an event is reported even though the original 
condition is no longer valid. Writing a logic ’1’ clears the bit. 
1:1
RW1C
0x0
overflow_status_bit:
Overflow Status Bit  
This status bit captures the overflow event from the PMD counter.This bit 
remains set once an event is reported even though the original condition is no 
longer valid. Writing a logic ’1’ clears the bit. 
0:0
RW
0x0
counter_reset:
Counter Reset  
Setting this bit resets the PMD counter, the associated adder storage register 
and the count mode state latch (see bits CNTMD) to the default state. It does 
not change the state of this PMR register, the event selections, or the value in 
the compare register. Note: This bit must be cleared by software, otherwise 
the counters remain in reset. There is also a reset bit in the PERFCON register 
which clears all PM registers including the PMR. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0
Bus:
0
Device:
3Function:0
Offset:
0x494, 0x498
Bit
Attr
Default
Description
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